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Commit 8fbb988a authored by Eric Kooistra's avatar Eric Kooistra
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Merge branch 'master' of git.astron.nl:rtsd/hdl

parents 8fec3630 770346f3
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applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/crc_generator.vhd
+ 3
− 1
View file @ 8fbb988a
...@@ -68,6 +68,8 @@ ...@@ -68,6 +68,8 @@
-- 2016-02-16 1.0 will Created -- 2016-02-16 1.0 will Created
-- 2019-10-15 1.1 Will Kamp Added support for i_stream.keep, generics to -- 2019-10-15 1.1 Will Kamp Added support for i_stream.keep, generics to
-- control bit reversal and CRC output XOR. -- control bit reversal and CRC output XOR.
-- 2024-02-27 1.2 R vd Walle Removed byte swap when G_BIT_REVERSE_OUT =
-- (ASTRON) true, only perform bit swap, no byte swap.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
library ieee; library ieee;
...@@ -243,7 +245,7 @@ begin -- architecture rtl ...@@ -243,7 +245,7 @@ begin -- architecture rtl
v_xor_crc := v_rb_crc xor g_XOR_CRC_OUT; v_xor_crc := v_rb_crc xor g_XOR_CRC_OUT;
if g_BIT_REVERSE_OUT then if g_BIT_REVERSE_OUT then
o_crc <= byte_swap(bit_swap(v_xor_crc)); o_crc <= bit_swap(v_xor_crc);
else else
o_crc <= v_xor_crc; o_crc <= v_xor_crc;
end if; end if;
......
applications/rdma_demo/libraries/rdma_packetiser/cocotb/tb_rdma_packetiser.py
+ 8
− 3
View file @ 8fbb988a
...@@ -42,6 +42,7 @@ from cocotb.utils import hexdump ...@@ -42,6 +42,7 @@ from cocotb.utils import hexdump
from cocotb.triggers import FallingEdge, Timer from cocotb.triggers import FallingEdge, Timer
from cocotb.clock import Clock from cocotb.clock import Clock
from cocotb.binary import BinaryValue from cocotb.binary import BinaryValue
from cocotb import logging
from dp_bus import DpStream from dp_bus import DpStream
from mm_bus import MMController from mm_bus import MMController
...@@ -98,9 +99,10 @@ def verify_mm_regs(actual_dict, exp_dict): ...@@ -98,9 +99,10 @@ def verify_mm_regs(actual_dict, exp_dict):
assert actual_dict[k].integer == v["value"], ( assert actual_dict[k].integer == v["value"], (
f'ERROR: Wrong value when reading back register, expected {k} = {v["value"]} but got {actual_dict[k]}') f'ERROR: Wrong value when reading back register, expected {k} = {v["value"]} but got {actual_dict[k]}')
async def send_multi_dp_packet(dp_stream: DpStream, data, n): async def send_multi_dp_packet(dp_stream: DpStream, data, n, gap_size_period = 0):
for i in range(n): for i in range(n):
await cocotb.start_soon(dp_stream.sosi_drv._driver_send(data)) await cocotb.start_soon(dp_stream.sosi_drv._driver_send(data))
await Timer(gap_size_period)
def carry_around_add(a, b): def carry_around_add(a, b):
c = a + b c = a + b
...@@ -172,6 +174,8 @@ def verify_header(hdr, exp_hdr): ...@@ -172,6 +174,8 @@ def verify_header(hdr, exp_hdr):
@cocotb.test() @cocotb.test()
async def tb_rdma_packetiser(dut): async def tb_rdma_packetiser(dut):
"""Try accessing the design. run with < run -a >""" """Try accessing the design. run with < run -a >"""
#dut._log.setLevel(logging.DEBUG)
# Constants # Constants
c_bsn_init = 17 # some bsn as starting bsn c_bsn_init = 17 # some bsn as starting bsn
n_bytes = dut.c_nof_byte.value n_bytes = dut.c_nof_byte.value
...@@ -180,6 +184,7 @@ async def tb_rdma_packetiser(dut): ...@@ -180,6 +184,7 @@ async def tb_rdma_packetiser(dut):
c_block_len = n_words * n_bytes c_block_len = n_words * n_bytes
c_nof_packets_in_msg = 5 c_nof_packets_in_msg = 5
c_dma_len = c_block_len * c_nof_packets_in_msg c_dma_len = c_block_len * c_nof_packets_in_msg
c_gap_size = 10
# Packet header definition and config # Packet header definition and config
hdr_dict = { hdr_dict = {
...@@ -272,7 +277,7 @@ async def tb_rdma_packetiser(dut): ...@@ -272,7 +277,7 @@ async def tb_rdma_packetiser(dut):
mm_rd = await read_mm_dict(reg_hdr_dat, hdr_dict) # read back MM registers mm_rd = await read_mm_dict(reg_hdr_dat, hdr_dict) # read back MM registers
verify_mm_regs(mm_rd, hdr_dict) # verify that the read (RW)registers are the same as what is written. verify_mm_regs(mm_rd, hdr_dict) # verify that the read (RW)registers are the same as what is written.
await FallingEdge(dut.dp_clk) # wait for falling edge/"negedge" await FallingEdge(dut.dp_clk) # wait for falling edge/"negedge"
cocotb.start_soon(send_multi_dp_packet(in_stream, snk_in_data, 10)) # Send DP packets cocotb.start_soon(send_multi_dp_packet(in_stream, snk_in_data, 10, c_gap_size * dpClock.period)) # Send DP packets
# Verify output packets # Verify output packets
for i in range(10): for i in range(10):
...@@ -318,7 +323,7 @@ async def tb_rdma_packetiser(dut): ...@@ -318,7 +323,7 @@ async def tb_rdma_packetiser(dut):
# ICRC could be calculated using the scapy library (if installed) with the code below. # ICRC could be calculated using the scapy library (if installed) with the code below.
# from scapy.layers.l2 import Ether # from scapy.layers.l2 import Ether
# from scapy.contrib.roce import BTH # for compute_icrc function # from scapy.contrib.roce import BTH # for compute_icrc function
# icrc = int.from_bytes(Ether(packet)['BTH'].compute_icrc(None), 'little') # exp_icrc = int.from_bytes(Ether(packet)['BTH'].compute_icrc(None), 'little')
icrc = int.from_bytes(packet[-4:], "big") icrc = int.from_bytes(packet[-4:], "big")
ones = (0xFF).to_bytes(1, 'little') ones = (0xFF).to_bytes(1, 'little')
pseudo_packet = ([ones] * 8 + [packet[14:15]] + pseudo_packet = ([ones] * 8 + [packet[14:15]] +
......
applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser.vhd
+ 74
− 83
View file @ 8fbb988a
...@@ -20,7 +20,9 @@ ...@@ -20,7 +20,9 @@
-- Author: R. van der Walle -- Author: R. van der Walle
-- Purpose: Packetizes an incoming data stream as RDMA "WRITE" packets. -- Purpose: Packetizes an incoming data stream as RDMA "WRITE" packets.
-- Description: see https://support.astron.nl/confluence/x/urT-Bg -- Description: see https://support.astron.nl/confluence/x/urT-Bg
-- -- Note: Due to the extra headers being prepended and the latency
-- that is introduced, a gap size of 10 clock cycles between
-- packets is necessary.
library IEEE, common_lib, dp_lib, eth_lib, rdma_icrc_external_lib; library IEEE, common_lib, dp_lib, eth_lib, rdma_icrc_external_lib;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all; use common_lib.common_pkg.all;
...@@ -30,6 +32,7 @@ use dp_lib.dp_stream_pkg.all; ...@@ -30,6 +32,7 @@ use dp_lib.dp_stream_pkg.all;
use dp_lib.dp_components_pkg.all; use dp_lib.dp_components_pkg.all;
use eth_lib.eth_pkg.all; use eth_lib.eth_pkg.all;
use eth_lib.eth_tester_pkg.all; use eth_lib.eth_tester_pkg.all;
use work.rdma_packetiser_pkg.all;
entity rdma_packetiser is entity rdma_packetiser is
generic ( generic (
...@@ -47,11 +50,6 @@ entity rdma_packetiser is ...@@ -47,11 +50,6 @@ entity rdma_packetiser is
reg_hdr_dat_copi : in t_mem_copi := c_mem_copi_rst; reg_hdr_dat_copi : in t_mem_copi := c_mem_copi_rst;
reg_hdr_dat_cipo : out t_mem_cipo; reg_hdr_dat_cipo : out t_mem_cipo;
reg_bsn_monitor_v2_rdma_packetiser_input_copi : in t_mem_copi := c_mem_copi_rst;
reg_bsn_monitor_v2_rdma_packetiser_input_cipo : out t_mem_cipo;
reg_bsn_monitor_v2_rdma_packetiser_output_copi : in t_mem_copi := c_mem_copi_rst;
reg_bsn_monitor_v2_rdma_packetiser_output_cipo : out t_mem_cipo;
snk_in : in t_dp_sosi := c_dp_sosi_rst; snk_in : in t_dp_sosi := c_dp_sosi_rst;
snk_out : out t_dp_siso := c_dp_siso_rdy; snk_out : out t_dp_siso := c_dp_siso_rdy;
...@@ -66,31 +64,26 @@ architecture str of rdma_packetiser is ...@@ -66,31 +64,26 @@ architecture str of rdma_packetiser is
constant c_nof_byte : natural := 64; constant c_nof_byte : natural := 64;
constant c_data_w : natural := c_nof_byte * c_byte_w; constant c_data_w : natural := c_nof_byte * c_byte_w;
constant c_max_packet_size : natural := ceil_div(9000, c_nof_byte); constant c_max_packet_size : natural := ceil_div(9000, c_nof_byte);
-- dp_offload_tx_v3 needs 8 clock cycles (minimum) to prepend headers
-- even if the header is < 8 words
constant c_latency_dp_offload_tx : natural := 8;
constant c_dp_fifo_latency : natural := 3;
constant c_fifo_size : natural := c_dp_fifo_latency + c_latency_dp_offload_tx;
signal dp_xonoff_sosi : t_dp_sosi := c_dp_sosi_rst; signal eth_hdr : std_logic_vector(1023 downto 0) := (others => '0');
signal dp_xonoff_siso : t_dp_siso := c_dp_siso_rdy;
signal dp_fifo_data_sosi : t_dp_sosi := c_dp_sosi_rst; signal dp_fifo_data_sosi : t_dp_sosi := c_dp_sosi_rst;
signal dp_fifo_data_siso : t_dp_siso := c_dp_siso_rdy; signal dp_fifo_data_siso : t_dp_siso := c_dp_siso_rdy;
signal dp_fifo_eth_hdr_sosi : t_dp_sosi := c_dp_sosi_rst;
signal dp_fifo_eth_hdr_siso : t_dp_siso := c_dp_siso_rdy;
signal assemble_header_sosi : t_dp_sosi := c_dp_sosi_rst; signal assemble_header_sosi : t_dp_sosi := c_dp_sosi_rst;
signal assemble_header_siso : t_dp_siso := c_dp_siso_rdy; signal assemble_header_siso : t_dp_siso := c_dp_siso_rdy;
signal icrc_sosi : t_dp_sosi := c_dp_sosi_rst; signal icrc_sosi : t_dp_sosi := c_dp_sosi_rst;
signal icrc_siso : t_dp_siso := c_dp_siso_rdy; signal icrc_siso : t_dp_siso := c_dp_siso_rdy;
begin begin
-- dp_xonoff to prevent fifo overflow -- dp_fifo for prepending RDMA headers. dp_offload_tx_v3 needs 8 clock cycles
u_dp_xonoff : entity dp_lib.dp_xonoff -- (minimum) to prepend headers even if the header is < 8 words.
port map ( u_dp_fifo_data : entity dp_lib.dp_fifo_sc
rst => dp_rst,
clk => dp_clk,
in_siso => snk_out,
in_sosi => snk_in,
out_siso => dp_xonoff_siso,
out_sosi => dp_xonoff_sosi
);
-- dp_fifo_fill_eop
u_dp_fifo_data : entity dp_lib.dp_fifo_fill_eop_sc
generic map ( generic map (
g_data_w => c_data_w, g_data_w => c_data_w,
g_empty_w => c_byte_w, g_empty_w => c_byte_w,
...@@ -98,8 +91,7 @@ begin ...@@ -98,8 +91,7 @@ begin
g_use_empty => true, g_use_empty => true,
g_use_bsn => true, g_use_bsn => true,
g_use_sync => true, g_use_sync => true,
g_fifo_size => c_max_packet_size * 2, g_fifo_size => c_fifo_size,
g_fifo_fill => c_max_packet_size,
g_fifo_rl => 1, g_fifo_rl => 1,
g_fifo_af_margin => 0, g_fifo_af_margin => 0,
g_fifo_af_xon => 0 g_fifo_af_xon => 0
...@@ -107,34 +99,12 @@ begin ...@@ -107,34 +99,12 @@ begin
port map ( port map (
clk => dp_clk, clk => dp_clk,
rst => dp_rst, rst => dp_rst,
snk_in => dp_xonoff_sosi, snk_in => snk_in,
snk_out => dp_xonoff_siso, snk_out => snk_out,
src_out => dp_fifo_data_sosi, src_out => dp_fifo_data_sosi,
src_in => dp_fifo_data_siso src_in => dp_fifo_data_siso
); );
-- mms_dp_bsn_monitor_v2
u_bsn_mon_input : entity dp_lib.mms_dp_bsn_monitor_v2
generic map (
g_nof_streams => 1,
g_cross_clock_domain => g_cross_clock_domain,
g_sync_timeout => g_sync_timeout
)
port map (
-- Memory-mapped clock domain
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mosi => reg_bsn_monitor_v2_rdma_packetiser_input_copi,
reg_miso => reg_bsn_monitor_v2_rdma_packetiser_input_cipo,
-- Streaming clock domain
dp_rst => dp_rst,
dp_clk => dp_clk,
ref_sync => snk_in.sync,
in_sosi_arr(0) => dp_fifo_data_sosi
);
u_rdma_assemble_header : entity work.rdma_packetiser_assemble_header u_rdma_assemble_header : entity work.rdma_packetiser_assemble_header
generic map ( generic map (
g_data_w => c_data_w g_data_w => c_data_w
...@@ -143,8 +113,8 @@ begin ...@@ -143,8 +113,8 @@ begin
-- Clocks and reset -- Clocks and reset
mm_rst => mm_rst, mm_rst => mm_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
st_rst => dp_rst, dp_rst => dp_rst,
st_clk => dp_clk, dp_clk => dp_clk,
-- Streaming interfaces -- Streaming interfaces
snk_in => dp_fifo_data_sosi, snk_in => dp_fifo_data_sosi,
...@@ -157,7 +127,10 @@ begin ...@@ -157,7 +127,10 @@ begin
reg_hdr_dat_cipo => reg_hdr_dat_cipo, reg_hdr_dat_cipo => reg_hdr_dat_cipo,
-- block length in nof octets -- block length in nof octets
block_len => block_len block_len => block_len,
-- ETH header to be prepended after icrc computation
eth_hdr => eth_hdr
); );
u_icrc_append : entity rdma_icrc_external_lib.append_crc_dp_wrapper u_icrc_append : entity rdma_icrc_external_lib.append_crc_dp_wrapper
...@@ -172,29 +145,47 @@ begin ...@@ -172,29 +145,47 @@ begin
out_dp_siso => icrc_siso out_dp_siso => icrc_siso
); );
-- mms_dp_bsn_monitor_v2 -- dp_fifo after icrc as icrc_append cannot handle backpressure.
u_bsn_mon_output : entity dp_lib.mms_dp_bsn_monitor_v2 -- also buffer for prepending the eth header, .
u_dp_fifo_eth_hdr : entity dp_lib.dp_fifo_sc
generic map ( generic map (
g_nof_streams => 1, g_data_w => c_data_w,
g_cross_clock_domain => g_cross_clock_domain, g_empty_w => c_byte_w,
g_sync_timeout => g_sync_timeout g_bsn_w => 64,
g_use_empty => true,
g_use_bsn => true,
g_use_sync => true,
g_fifo_size => c_fifo_size,
g_fifo_rl => 1,
g_fifo_af_margin => 0,
g_fifo_af_xon => 0
) )
port map ( port map (
-- Memory-mapped clock domain clk => dp_clk,
mm_rst => mm_rst, rst => dp_rst,
mm_clk => mm_clk, snk_in => icrc_sosi,
reg_mosi => reg_bsn_monitor_v2_rdma_packetiser_output_copi, snk_out => icrc_siso,
reg_miso => reg_bsn_monitor_v2_rdma_packetiser_output_cipo, src_out => dp_fifo_eth_hdr_sosi,
src_in => dp_fifo_eth_hdr_siso
);
-- Streaming clock domain -- dp_offload_tx_v3
u_dp_offload_tx : entity dp_lib.dp_offload_tx_v3
generic map (
g_nof_streams => 1,
g_data_w => c_data_w,
g_symbol_w => c_octet_w,
g_hdr_field_arr => c_rdma_packetiser_eth_hdr_field_arr,
g_hdr_field_sel => c_rdma_packetiser_eth_hdr_field_sel,
g_pipeline_ready => true
)
port map (
dp_rst => dp_rst, dp_rst => dp_rst,
dp_clk => dp_clk, dp_clk => dp_clk,
ref_sync => snk_in.sync, snk_in_arr(0) => dp_fifo_eth_hdr_sosi,
snk_out_arr(0) => dp_fifo_eth_hdr_siso,
in_sosi_arr(0) => icrc_sosi src_out_arr(0) => src_out,
src_in_arr(0) => src_in,
hdr_fields_in_arr(0) => eth_hdr
); );
src_out <= icrc_sosi;
icrc_siso <= src_in;
end str; end str;
applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_assemble_header.vhd
+ 48
− 42
View file @ 8fbb988a
...@@ -72,8 +72,8 @@ entity rdma_packetiser_assemble_header is ...@@ -72,8 +72,8 @@ entity rdma_packetiser_assemble_header is
); );
port ( port (
-- Clocks and reset -- Clocks and reset
st_clk : in std_logic; dp_clk : in std_logic;
st_rst : in std_logic; dp_rst : in std_logic;
mm_clk : in std_logic; mm_clk : in std_logic;
mm_rst : in std_logic; mm_rst : in std_logic;
...@@ -87,7 +87,10 @@ entity rdma_packetiser_assemble_header is ...@@ -87,7 +87,10 @@ entity rdma_packetiser_assemble_header is
src_out : out t_dp_sosi := c_dp_sosi_rst; src_out : out t_dp_sosi := c_dp_sosi_rst;
src_in : in t_dp_siso := c_dp_siso_rdy; src_in : in t_dp_siso := c_dp_siso_rdy;
block_len : in std_logic_vector(c_halfword_w - 1 downto 0) -- in octets block_len : in std_logic_vector(c_halfword_w - 1 downto 0); -- in octets
eth_hdr : out std_logic_vector(1023 downto 0) := (others => '0')
); );
end rdma_packetiser_assemble_header; end rdma_packetiser_assemble_header;
...@@ -173,8 +176,8 @@ begin ...@@ -173,8 +176,8 @@ begin
start_address <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_start_address" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_start_address" )); start_address <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_start_address" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_start_address" ));
-- State machine to derive RDMA header fields. -- State machine to derive RDMA header fields.
q <= d when rising_edge(st_clk); q <= d when rising_edge(dp_clk);
p_comb : process(st_rst, q, snk_in, nof_packets_in_msg, start_address, nof_msg, immediate_data, dma_len, block_len, use_immediate) p_comb : process(dp_rst, q, snk_in, nof_packets_in_msg, start_address, nof_msg, immediate_data, dma_len, block_len, use_immediate)
variable v : t_reg; variable v : t_reg;
begin begin
v := q; v := q;
...@@ -249,7 +252,7 @@ begin ...@@ -249,7 +252,7 @@ begin
v.nof_packets_in_msg := to_uint(nof_packets_in_msg); v.nof_packets_in_msg := to_uint(nof_packets_in_msg);
end if; end if;
if st_rst = '1' then if dp_rst = '1' then
v := c_reg_rst; v := c_reg_rst;
end if; end if;
...@@ -278,8 +281,8 @@ begin ...@@ -278,8 +281,8 @@ begin
g_sel_ctrl_pkt => true g_sel_ctrl_pkt => true
) )
port map ( port map (
rst => st_rst, rst => dp_rst,
clk => st_clk, clk => dp_clk,
sel_ctrl => q.sel_ctrl, sel_ctrl => q.sel_ctrl,
...@@ -304,6 +307,9 @@ begin ...@@ -304,6 +307,9 @@ begin
p_wire_headers : process(hdr_fields_slv_out_mm, use_msg_cnt_as_immediate, q) p_wire_headers : process(hdr_fields_slv_out_mm, use_msg_cnt_as_immediate, q)
begin begin
-- set headers. -- set headers.
eth_hdr <= field_select_subset(c_rdma_packetiser_eth_hdr_field_arr,
c_rdma_packetiser_mm_field_arr,
hdr_fields_slv_out_mm);
hdr_fields_slv_in_first <= field_select_subset(c_rdma_packetiser_first_hdr_field_arr, hdr_fields_slv_in_first <= field_select_subset(c_rdma_packetiser_first_hdr_field_arr,
c_rdma_packetiser_mm_field_arr, c_rdma_packetiser_mm_field_arr,
hdr_fields_slv_out_mm); hdr_fields_slv_out_mm);
...@@ -337,8 +343,8 @@ begin ...@@ -337,8 +343,8 @@ begin
g_pipeline_ready => true g_pipeline_ready => true
) )
port map ( port map (
dp_rst => st_rst, dp_rst => dp_rst,
dp_clk => st_clk, dp_clk => dp_clk,
snk_in_arr(0) => eth_ip_offload_first_snk_in, snk_in_arr(0) => eth_ip_offload_first_snk_in,
snk_out_arr(0) => eth_ip_offload_first_snk_out, snk_out_arr(0) => eth_ip_offload_first_snk_out,
src_out_arr(0) => eth_ip_offload_first_src_out, src_out_arr(0) => eth_ip_offload_first_src_out,
...@@ -359,8 +365,8 @@ begin ...@@ -359,8 +365,8 @@ begin
g_pipeline_ready => true g_pipeline_ready => true
) )
port map ( port map (
dp_rst => st_rst, dp_rst => dp_rst,
dp_clk => st_clk, dp_clk => dp_clk,
snk_in_arr(0) => eth_ip_offload_mid_snk_in, snk_in_arr(0) => eth_ip_offload_mid_snk_in,
snk_out_arr(0) => eth_ip_offload_mid_snk_out, snk_out_arr(0) => eth_ip_offload_mid_snk_out,
src_out_arr(0) => eth_ip_offload_mid_src_out, src_out_arr(0) => eth_ip_offload_mid_src_out,
...@@ -381,8 +387,8 @@ begin ...@@ -381,8 +387,8 @@ begin
g_pipeline_ready => true g_pipeline_ready => true
) )
port map ( port map (
dp_rst => st_rst, dp_rst => dp_rst,
dp_clk => st_clk, dp_clk => dp_clk,
snk_in_arr(0) => eth_ip_offload_last_snk_in, snk_in_arr(0) => eth_ip_offload_last_snk_in,
snk_out_arr(0) => eth_ip_offload_last_snk_out, snk_out_arr(0) => eth_ip_offload_last_snk_out,
src_out_arr(0) => eth_ip_offload_last_src_out, src_out_arr(0) => eth_ip_offload_last_src_out,
...@@ -403,8 +409,8 @@ begin ...@@ -403,8 +409,8 @@ begin
g_pipeline_ready => true g_pipeline_ready => true
) )
port map ( port map (
dp_rst => st_rst, dp_rst => dp_rst,
dp_clk => st_clk, dp_clk => dp_clk,
snk_in_arr(0) => eth_ip_offload_wo_snk_in, snk_in_arr(0) => eth_ip_offload_wo_snk_in,
snk_out_arr(0) => eth_ip_offload_wo_snk_out, snk_out_arr(0) => eth_ip_offload_wo_snk_out,
src_out_arr(0) => eth_ip_offload_wo_src_out, src_out_arr(0) => eth_ip_offload_wo_src_out,
...@@ -418,8 +424,8 @@ begin ...@@ -418,8 +424,8 @@ begin
-- DP pipeline to correct for state machine latency -- DP pipeline to correct for state machine latency
u_dp_pipeline : entity dp_lib.dp_pipeline u_dp_pipeline : entity dp_lib.dp_pipeline
port map ( port map (
rst => st_rst, rst => dp_rst,
clk => st_clk, clk => dp_clk,
snk_in => snk_in, snk_in => snk_in,
src_out => dp_pipeline_src_out src_out => dp_pipeline_src_out
); );
...@@ -437,8 +443,8 @@ begin ...@@ -437,8 +443,8 @@ begin
port map ( port map (
mm_rst => mm_rst, mm_rst => mm_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
dp_rst => st_rst, dp_rst => dp_rst,
dp_clk => st_clk, dp_clk => dp_clk,
reg_hdr_dat_mosi => reg_hdr_dat_copi, reg_hdr_dat_mosi => reg_hdr_dat_copi,
reg_hdr_dat_miso => reg_hdr_dat_cipo, reg_hdr_dat_miso => reg_hdr_dat_cipo,
snk_in_arr(0) => dp_pipeline_src_out, snk_in_arr(0) => dp_pipeline_src_out,
...@@ -470,8 +476,8 @@ begin ...@@ -470,8 +476,8 @@ begin
g_fifo_fill => array_init(0, c_nof_offload) g_fifo_fill => array_init(0, c_nof_offload)
) )
port map ( port map (
rst => st_rst, rst => dp_rst,
clk => st_clk, clk => dp_clk,
sel_ctrl => q.sel_ctrl_delayed, sel_ctrl => q.sel_ctrl_delayed,
snk_in_arr => dp_mux_snk_in_arr, snk_in_arr => dp_mux_snk_in_arr,
snk_out_arr => dp_mux_snk_out_arr, snk_out_arr => dp_mux_snk_out_arr,
......
applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd
+ 34
− 36
View file @ 8fbb988a
...@@ -94,9 +94,9 @@ package rdma_packetiser_pkg is ...@@ -94,9 +94,9 @@ package rdma_packetiser_pkg is
constant c_rdma_packetiser_mm_field_arr : t_common_field_arr( constant c_rdma_packetiser_mm_field_arr : t_common_field_arr(
c_rdma_packetiser_mm_nof_fields - 1 downto 0) := ( c_rdma_packetiser_mm_nof_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- set by M&C ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ), -- set by M&C ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ), -- fixed ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), -- fixed ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), -- fixed
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), -- fixed ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), -- fixed
...@@ -146,19 +146,25 @@ package rdma_packetiser_pkg is ...@@ -146,19 +146,25 @@ package rdma_packetiser_pkg is
constant c_rdma_packetiser_reg_mm_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_packetiser_mm_field_arr, c_word_w)); constant c_rdma_packetiser_reg_mm_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_packetiser_mm_field_arr, c_word_w));
constant c_rdma_packetiser_reg_mm_dat_addr_span : natural := 2**c_rdma_packetiser_reg_mm_dat_addr_w; constant c_rdma_packetiser_reg_mm_dat_addr_span : natural := 2**c_rdma_packetiser_reg_mm_dat_addr_w;
-- ETH header
-- Handeled seperate from the other headers as the ethernet header must be excluded from the icrc checksum computation.
constant c_rdma_packetiser_eth_hdr_nof_fields : natural := 3 ;
constant c_rdma_packetiser_eth_hdr_field_sel : std_logic_vector(c_rdma_packetiser_eth_hdr_nof_fields - 1 downto 0) := (others => '0');
constant c_rdma_packetiser_eth_hdr_field_arr : t_common_field_arr(
c_rdma_packetiser_eth_hdr_nof_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") )
);
-- RoCEv2 header for first packets and write only packets without immediate data -- RoCEv2 header for first packets and write only packets without immediate data
-- ETH + IP + UDP + Base Transport Header (BTH) + RDMA Extended Transport Header (RETH) -- IP + UDP + Base Transport Header (BTH) + RDMA Extended Transport Header (RETH)
constant c_rdma_packetiser_first_nof_hdr_fields : natural := 3 + 12 + 4 + 13 + 3; constant c_rdma_packetiser_first_nof_hdr_fields : natural := 12 + 4 + 13 + 3;
constant c_rdma_packetiser_first_hdr_field_sel : std_logic_vector(c_rdma_packetiser_first_nof_hdr_fields - 1 downto 0) := (others => '0'); constant c_rdma_packetiser_first_hdr_field_sel : std_logic_vector(c_rdma_packetiser_first_nof_hdr_fields - 1 downto 0) := (others => '0');
constant c_rdma_packetiser_first_hdr_field_arr : t_common_field_arr( constant c_rdma_packetiser_first_hdr_field_arr : t_common_field_arr(
c_rdma_packetiser_first_nof_hdr_fields - 1 downto 0) := ( c_rdma_packetiser_first_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
...@@ -198,16 +204,12 @@ package rdma_packetiser_pkg is ...@@ -198,16 +204,12 @@ package rdma_packetiser_pkg is
); );
-- RoCEv2 header for middle packets and last packets without immediate data. -- RoCEv2 header for middle packets and last packets without immediate data.
-- ETH + IP + UDP + Base Transport Header (BTH) -- IP + UDP + Base Transport Header (BTH)
constant c_rdma_packetiser_mid_nof_hdr_fields : natural := 3 + 12 + 4 + 13; constant c_rdma_packetiser_mid_nof_hdr_fields : natural := 12 + 4 + 13;
constant c_rdma_packetiser_mid_hdr_field_sel : std_logic_vector(c_rdma_packetiser_mid_nof_hdr_fields - 1 downto 0) := (others => '0'); constant c_rdma_packetiser_mid_hdr_field_sel : std_logic_vector(c_rdma_packetiser_mid_nof_hdr_fields - 1 downto 0) := (others => '0');
constant c_rdma_packetiser_mid_hdr_field_arr : t_common_field_arr( constant c_rdma_packetiser_mid_hdr_field_arr : t_common_field_arr(
c_rdma_packetiser_mid_nof_hdr_fields - 1 downto 0) := ( c_rdma_packetiser_mid_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
...@@ -242,16 +244,12 @@ package rdma_packetiser_pkg is ...@@ -242,16 +244,12 @@ package rdma_packetiser_pkg is
); );
-- RoCEv2 header for last packets with immediate data -- RoCEv2 header for last packets with immediate data
-- ETH + IP + UDP + Base Transport Header (BTH) + immediate data -- IP + UDP + Base Transport Header (BTH) + immediate data
constant c_rdma_packetiser_last_nof_hdr_fields : natural := 3 + 12 + 4 + 13 + 1; constant c_rdma_packetiser_last_nof_hdr_fields : natural := 12 + 4 + 13 + 1;
constant c_rdma_packetiser_last_hdr_field_sel : std_logic_vector(c_rdma_packetiser_last_nof_hdr_fields - 1 downto 0) := (others => '0'); constant c_rdma_packetiser_last_hdr_field_sel : std_logic_vector(c_rdma_packetiser_last_nof_hdr_fields - 1 downto 0) := (others => '0');
constant c_rdma_packetiser_last_hdr_field_arr : t_common_field_arr( constant c_rdma_packetiser_last_hdr_field_arr : t_common_field_arr(
c_rdma_packetiser_last_nof_hdr_fields - 1 downto 0) := ( c_rdma_packetiser_last_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
...@@ -288,16 +286,12 @@ package rdma_packetiser_pkg is ...@@ -288,16 +286,12 @@ package rdma_packetiser_pkg is
); );
-- RoCEv2 header for write only packets with immediate data -- RoCEv2 header for write only packets with immediate data
-- ETH + IP + UDP + Base Transport Header (BTH) + RDMA Extended Transport Header (RETH) + immediate data -- IP + UDP + Base Transport Header (BTH) + RDMA Extended Transport Header (RETH) + immediate data
constant c_rdma_packetiser_wo_nof_hdr_fields : natural := 3 + 12 + 4 + 13 + 3 + 1; constant c_rdma_packetiser_wo_nof_hdr_fields : natural := 12 + 4 + 13 + 3 + 1;
constant c_rdma_packetiser_wo_hdr_field_sel : std_logic_vector(c_rdma_packetiser_wo_nof_hdr_fields - 1 downto 0) := (others => '0'); constant c_rdma_packetiser_wo_hdr_field_sel : std_logic_vector(c_rdma_packetiser_wo_nof_hdr_fields - 1 downto 0) := (others => '0');
constant c_rdma_packetiser_wo_hdr_field_arr : t_common_field_arr( constant c_rdma_packetiser_wo_hdr_field_arr : t_common_field_arr(
c_rdma_packetiser_wo_nof_hdr_fields - 1 downto 0) := ( c_rdma_packetiser_wo_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
...@@ -364,10 +358,12 @@ package body rdma_packetiser_pkg is ...@@ -364,10 +358,12 @@ package body rdma_packetiser_pkg is
variable v : t_rdma_packetiser_roce_header; variable v : t_rdma_packetiser_roce_header;
constant c_hdr_field_arr : t_common_field_arr := field_arr; constant c_hdr_field_arr : t_common_field_arr := field_arr;
begin begin
-- eth header -- eth header (optional)
if field_exists(c_hdr_field_arr, "eth_dst_mac") then -- eth header exists
v.eth.dst_mac := hdr_fields_raw(field_hi(c_hdr_field_arr, "eth_dst_mac") downto field_lo(c_hdr_field_arr, "eth_dst_mac")); v.eth.dst_mac := hdr_fields_raw(field_hi(c_hdr_field_arr, "eth_dst_mac") downto field_lo(c_hdr_field_arr, "eth_dst_mac"));
v.eth.src_mac := hdr_fields_raw(field_hi(c_hdr_field_arr, "eth_src_mac") downto field_lo(c_hdr_field_arr, "eth_src_mac")); v.eth.src_mac := hdr_fields_raw(field_hi(c_hdr_field_arr, "eth_src_mac") downto field_lo(c_hdr_field_arr, "eth_src_mac"));
v.eth.eth_type := hdr_fields_raw(field_hi(c_hdr_field_arr, "eth_type") downto field_lo(c_hdr_field_arr, "eth_type")); v.eth.eth_type := hdr_fields_raw(field_hi(c_hdr_field_arr, "eth_type") downto field_lo(c_hdr_field_arr, "eth_type"));
end if;
-- ip header -- ip header
v.ip.version := hdr_fields_raw(field_hi(c_hdr_field_arr, "ip_version") downto field_lo(c_hdr_field_arr, "ip_version")); v.ip.version := hdr_fields_raw(field_hi(c_hdr_field_arr, "ip_version") downto field_lo(c_hdr_field_arr, "ip_version"));
...@@ -426,10 +422,12 @@ package body rdma_packetiser_pkg is ...@@ -426,10 +422,12 @@ package body rdma_packetiser_pkg is
variable v : std_logic_vector(c_field_len-1 downto 0) := (others => '0'); variable v : std_logic_vector(c_field_len-1 downto 0) := (others => '0');
constant c_hdr_field_arr : t_common_field_arr := field_arr; constant c_hdr_field_arr : t_common_field_arr := field_arr;
begin begin
-- eth header -- eth header (optional)
if field_exists(c_hdr_field_arr, "eth_dst_mac") then -- eth header exists
v(field_hi(c_hdr_field_arr, "eth_dst_mac") downto field_lo(c_hdr_field_arr, "eth_dst_mac")) := hdr_fields.eth.dst_mac; v(field_hi(c_hdr_field_arr, "eth_dst_mac") downto field_lo(c_hdr_field_arr, "eth_dst_mac")) := hdr_fields.eth.dst_mac;
v(field_hi(c_hdr_field_arr, "eth_src_mac") downto field_lo(c_hdr_field_arr, "eth_src_mac")) := hdr_fields.eth.src_mac; v(field_hi(c_hdr_field_arr, "eth_src_mac") downto field_lo(c_hdr_field_arr, "eth_src_mac")) := hdr_fields.eth.src_mac;
v(field_hi(c_hdr_field_arr, "eth_type") downto field_lo(c_hdr_field_arr, "eth_type")) := hdr_fields.eth.eth_type; v(field_hi(c_hdr_field_arr, "eth_type") downto field_lo(c_hdr_field_arr, "eth_type")) := hdr_fields.eth.eth_type;
end if;
-- ip header -- ip header
v(field_hi(c_hdr_field_arr, "ip_version") downto field_lo(c_hdr_field_arr, "ip_version")) := hdr_fields.ip.version; v(field_hi(c_hdr_field_arr, "ip_version") downto field_lo(c_hdr_field_arr, "ip_version")) := hdr_fields.ip.version;
......
applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
+ 2
− 3
View file @ 8fbb988a
...@@ -229,7 +229,6 @@ begin ...@@ -229,7 +229,6 @@ begin
-- assign expected values to signal to view in wave window. -- assign expected values to signal to view in wave window.
-- defaults -- defaults
v_exp_rdma_header.eth.eth_type := x"0800";
v_exp_rdma_header.ip.version := to_uvec(4, 4); v_exp_rdma_header.ip.version := to_uvec(4, 4);
v_exp_rdma_header.ip.header_length := to_uvec(5, 4); v_exp_rdma_header.ip.header_length := to_uvec(5, 4);
v_exp_rdma_header.ip.flags := to_uvec(2, 3); v_exp_rdma_header.ip.flags := to_uvec(2, 3);
...@@ -279,8 +278,8 @@ begin ...@@ -279,8 +278,8 @@ begin
g_data_w => g_data_w g_data_w => g_data_w
) )
port map ( port map (
st_clk => dp_clk, dp_clk => dp_clk,
st_rst => dp_rst, dp_rst => dp_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
mm_rst => mm_rst, mm_rst => mm_rst,
......
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