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Added altera reference design for EMIF IP, placedin the unb2c folder as
it is used with Quartus 19.2. The pinning is taken from unb2b.
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- boards/uniboard2c/designs/altera_ref_designs/ddr4/ed_sim.qsys 2660 additions, 0 deletions...ds/uniboard2c/designs/altera_ref_designs/ddr4/ed_sim.qsys
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ed_synth.qsys 1913 additions, 0 deletions.../uniboard2c/designs/altera_ref_designs/ddr4/ed_synth.qsys
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_emif_0.ip 11387 additions, 0 deletions...esigns/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_emif_0.ip
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_global_reset_n_source.ip 286 additions, 0 deletions...ef_designs/ddr4/ip/ed_sim/ed_sim_global_reset_n_source.ip
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_global_reset_n_splitter.ip 291 additions, 0 deletions..._designs/ddr4/ip/ed_sim/ed_sim_global_reset_n_splitter.ip
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_mem.ip 9343 additions, 0 deletions...c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_mem.ip
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_pll_ref_clk_source.ip 223 additions, 0 deletions...a_ref_designs/ddr4/ip/ed_sim/ed_sim_pll_ref_clk_source.ip
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_sim_checker.ip 627 additions, 0 deletions...s/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_sim_checker.ip
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_tg.ip 10386 additions, 0 deletions...2c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_tg.ip
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ip/ed_synth/ed_synth_emif_0.ip 11387 additions, 0 deletions...ns/altera_ref_designs/ddr4/ip/ed_synth/ed_synth_emif_0.ip
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ip/ed_synth/ed_synth_global_reset_n_splitter.ip 291 additions, 0 deletions...igns/ddr4/ip/ed_synth/ed_synth_global_reset_n_splitter.ip
- boards/uniboard2c/designs/altera_ref_designs/ddr4/ip/ed_synth/ed_synth_tg.ip 10386 additions, 0 deletions...esigns/altera_ref_designs/ddr4/ip/ed_synth/ed_synth_tg.ip
- boards/uniboard2c/designs/altera_ref_designs/ddr4/make_qii_design.tcl 151 additions, 0 deletions...ard2c/designs/altera_ref_designs/ddr4/make_qii_design.tcl
- boards/uniboard2c/designs/altera_ref_designs/ddr4/make_sim_design.tcl 176 additions, 0 deletions...ard2c/designs/altera_ref_designs/ddr4/make_sim_design.tcl
- boards/uniboard2c/designs/altera_ref_designs/ddr4/params.tcl 1741 additions, 0 deletionsboards/uniboard2c/designs/altera_ref_designs/ddr4/params.tcl
- boards/uniboard2c/designs/altera_ref_designs/ddr4/qii/ed_synth.archive.rpt 266 additions, 0 deletions.../designs/altera_ref_designs/ddr4/qii/ed_synth.archive.rpt
- boards/uniboard2c/designs/altera_ref_designs/ddr4/qii/ed_synth.asm.rpt 150 additions, 0 deletions...rd2c/designs/altera_ref_designs/ddr4/qii/ed_synth.asm.rpt
- boards/uniboard2c/designs/altera_ref_designs/ddr4/qii/ed_synth.done 1 addition, 0 deletions...board2c/designs/altera_ref_designs/ddr4/qii/ed_synth.done
- boards/uniboard2c/designs/altera_ref_designs/ddr4/qii/ed_synth.fit.finalize.rpt 68 additions, 0 deletions...gns/altera_ref_designs/ddr4/qii/ed_synth.fit.finalize.rpt
- boards/uniboard2c/designs/altera_ref_designs/ddr4/qii/ed_synth.fit.place.rpt 726 additions, 0 deletions...esigns/altera_ref_designs/ddr4/qii/ed_synth.fit.place.rpt
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