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Commit 8f810e64 authored by Pepping's avatar Pepping
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-Removed the io_ddr instance. 

-Updated port map to interface with external io_ddr
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libraries/base/reorder/src/vhdl/reorder_transpose.vhd
+ 42
− 107
View file @ 8f810e64
......@@ -20,10 +20,9 @@
--
--------------------------------------------------------------------------------
LIBRARY IEEE, technology_lib, common_lib, dp_lib, io_ddr_lib, tech_ddr_lib;
LIBRARY IEEE, common_lib, dp_lib, io_ddr_lib, tech_ddr_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
......@@ -33,7 +32,6 @@ USE work.reorder_pkg.ALL;
ENTITY reorder_transpose IS
GENERIC(
g_sim : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr;
g_nof_streams : NATURAL := 4;
g_in_dat_w : NATURAL := 8;
......@@ -61,31 +59,28 @@ ENTITY reorder_transpose IS
-- Memory Mapped
ram_ss_ss_transp_mosi : IN t_mem_mosi; -- channel select control
ram_ss_ss_transp_miso : OUT t_mem_miso;
-- Control interface to the external memory
dvr_miso : IN t_mem_ctlr_miso;
dvr_mosi : OUT t_mem_ctlr_mosi;
ser_term_ctrl_out : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
par_term_ctrl_out : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
ser_term_ctrl_in : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
par_term_ctrl_in : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
phy_in : IN t_tech_ddr_phy_in := c_tech_ddr_phy_in_x;
phy_io : INOUT t_tech_ddr_phy_io;
phy_ou : OUT t_tech_ddr_phy_ou
-- Data interface to the external memory
to_mem_src_out : OUT t_dp_sosi;
to_mem_src_in : IN t_dp_siso;
from_mem_snk_in : IN t_dp_sosi;
from_mem_snk_out : OUT t_dp_siso := c_dp_siso_rdy
);
END reorder_transpose;
ARCHITECTURE str OF reorder_transpose IS
CONSTANT c_min_fifo_size : POSITIVE := 256;
CONSTANT c_blocksize : POSITIVE := g_reorder_seq.wr_nof_chunks * (g_reorder_seq.wr_chunksize + g_reorder_seq.gapsize);
CONSTANT c_pagesize : POSITIVE := g_reorder_seq.nof_blocks * c_blocksize;
CONSTANT c_mem_size : POSITIVE := 2*c_pagesize;
CONSTANT c_mem_size_w : POSITIVE := ceil_log2(c_mem_size);
CONSTANT c_wr_fifo_depth : NATURAL := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);--c_blocksize * 2;
CONSTANT c_rd_fifo_depth : NATURAL := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);--c_blocksize * 2;
CONSTANT c_total_data_w : NATURAL := g_nof_streams*g_in_dat_w;
CONSTANT c_complex_data_w : NATURAL := c_total_data_w*c_nof_complex;
CONSTANT c_data_w : NATURAL := sel_a_b(g_use_complex, c_complex_data_w, c_total_data_w);
......@@ -109,17 +104,11 @@ ARCHITECTURE str OF reorder_transpose IS
SIGNAL dvr_nof_data : STD_LOGIC_VECTOR(c_mem_size_w-1 DOWNTO 0);
SIGNAL dvr_wr_flush_en : STD_LOGIC;
SIGNAL transpose_in_sosi : t_dp_sosi;
SIGNAL transpose_in_siso : t_dp_siso;
SIGNAL transpose_out_sosi : t_dp_sosi;
SIGNAL to_mem_src_out_i : t_dp_sosi;
SIGNAL block_gen_out_sosi : t_dp_sosi;
SIGNAL pipeline_out_sosi : t_dp_sosi;
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
SIGNAL sync_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
SIGNAL wr_req : STD_LOGIC;
SIGNAL rd_req_i : STD_LOGIC;
......@@ -132,9 +121,6 @@ ARCHITECTURE str OF reorder_transpose IS
SIGNAL nxt_mon_nof_sop : STD_LOGIC_VECTOR(c_cnt_sop_w-1 DOWNTO 0);
SIGNAL sync_ok_in : STD_LOGIC;
SIGNAL sync_ok_out : STD_LOGIC;
SIGNAL ctlr_clk : STD_LOGIC;
SIGNAL ctlr_rst : STD_LOGIC;
BEGIN
......@@ -149,15 +135,15 @@ BEGIN
END PROCESS;
END GENERATE;
-- g_merge_in_data : IF g_use_complex = FALSE GENERATE
-- merge_input : PROCESS(snk_in_arr)
-- BEGIN
-- transpose_in_sosi <= snk_in_arr(0);
-- FOR i IN 0 TO g_nof_streams-1 LOOP
-- transpose_in_sosi.data((i+1)*g_in_dat_w-1 DOWNTO i*g_in_dat_w) <= snk_in_arr(i).data(g_in_dat_w-1 DOWNTO 0);
-- END LOOP;
-- END PROCESS;
-- END GENERATE;
g_merge_in_data : IF g_use_complex = FALSE GENERATE
PROCESS(snk_in_arr)
BEGIN
ss_in_sosi <= snk_in_arr(0);
FOR i IN 0 TO g_nof_streams-1 LOOP
ss_in_sosi.data((i+1)*g_in_dat_w-1 DOWNTO i*g_in_dat_w) <= snk_in_arr(i).data(g_in_dat_w-1 DOWNTO 0);
END LOOP;
END PROCESS;
END GENERATE;
gen_pre_transpose : IF g_ena_pre_transp = TRUE GENERATE
u_single_ss : ENTITY work.ss
......@@ -182,82 +168,29 @@ BEGIN
input_sosi => ss_in_sosi,
input_siso => ss_in_siso,
output_sosi => transpose_in_sosi,
output_siso => transpose_in_siso
output_sosi => to_mem_src_out_i,
output_siso => to_mem_src_in
);
END GENERATE;
END GENERATE;
to_mem_src_out <= to_mem_src_out_i;
gen_not_pre_transpose : IF g_ena_pre_transp = FALSE GENERATE
transpose_in_sosi <= ss_in_sosi;
ss_in_siso <= transpose_in_siso;
to_mem_src_out_i <= ss_in_sosi;
ss_in_siso <= to_mem_src_in;
END GENERATE;
g_siso : FOR J IN 0 TO g_nof_streams-1 GENERATE
snk_out_arr(J) <= ss_in_siso;
END GENERATE;
u_ddr3: ENTITY io_ddr_lib.io_ddr
GENERIC MAP(
g_sim => g_sim,
g_technology => g_technology, -- : NATURAL := c_tech_select_default;
g_tech_ddr => g_tech_ddr, -- : t_c_tech_ddr;
g_cross_domain_dvr_ctlr => FALSE, --TRUE, -- : BOOLEAN := TRUE;
g_wr_data_w => c_data_w, -- : NATURAL := 32;
g_wr_fifo_depth => c_wr_fifo_depth, -- : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
g_rd_fifo_depth => c_rd_fifo_depth, -- : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
g_rd_data_w => c_data_w, -- : NATURAL := 32;
g_wr_flush_mode => "SYN", -- : STRING := "VAL"; -- "VAL", "SOP", "SYN"
g_wr_flush_use_channel => FALSE, -- : BOOLEAN := FALSE;
g_wr_flush_start_channel => 0, -- : NATURAL := 0;
g_wr_flush_nof_channels => 1 -- : POSITIVE := 1
)
PORT MAP (
-- DDR reference clock
ctlr_ref_clk => dp_clk,
ctlr_ref_rst => dp_rst,
-- DDR controller clock domain
ctlr_clk_out => ctlr_clk,
ctlr_rst_out => ctlr_rst,
ctlr_clk_in => ctlr_clk, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
ctlr_rst_in => ctlr_rst, -- connect ctlr_rst_out to ctlr_rst_in at top level
-- Driver clock domain
dvr_clk => dp_clk,
dvr_rst => dp_rst,
dvr_miso => ctlr_dvr_miso,
dvr_mosi => ctlr_dvr_mosi,
-- Write FIFO clock domain
wr_clk => dp_clk,
wr_rst => dp_rst,
wr_fifo_usedw => OPEN,
wr_sosi => transpose_in_sosi,
wr_siso => transpose_in_siso,
-- Read FIFO clock domain
rd_clk => dp_clk,
rd_rst => dp_rst,
rd_fifo_usedw => OPEN,
rd_sosi => transpose_out_sosi,
rd_siso => src_in_arr(0),
phy_in => phy_in,
phy_io => phy_io,
phy_ou => phy_ou
);
-- Map original dvr interface signals to t_mem_ctlr_mosi/miso
dvr_done <= ctlr_dvr_miso.done; -- Requested wr or rd sequence is done
ctlr_dvr_mosi.burstbegin <= dvr_en;
ctlr_dvr_mosi.wr <= dvr_wr_not_rd; -- No need to use dvr_mosi.rd
ctlr_dvr_mosi.address <= RESIZE_MEM_CTLR_ADDRESS(dvr_start_address);
ctlr_dvr_mosi.burstsize <= RESIZE_MEM_CTLR_BURSTSIZE(dvr_nof_data);
ctlr_dvr_mosi.flush <= dvr_wr_flush_en;
dvr_done <= dvr_miso.done; -- Requested wr or rd sequence is done
dvr_mosi.burstbegin <= dvr_en;
dvr_mosi.wr <= dvr_wr_not_rd; -- No need to use dvr_mosi.rd
dvr_mosi.address <= RESIZE_MEM_CTLR_ADDRESS(dvr_start_address);
dvr_mosi.burstsize <= RESIZE_MEM_CTLR_BURSTSIZE(dvr_nof_data);
dvr_mosi.flush <= dvr_wr_flush_en;
dvr_wr_flush_en <= NOT(sync_ok_out);
......@@ -289,13 +222,13 @@ BEGIN
PORT MAP (
rst => dp_rst,
clk => dp_clk,
cnt_clr => transpose_in_sosi.sync,
cnt_en => transpose_in_sosi.sop,
cnt_clr => to_mem_src_out_i.sync,
cnt_en => to_mem_src_out_i.sop,
count => cnt_sop
);
nof_sop <= INCR_UVEC(cnt_sop, 1); -- +1 because the sop at the sync also counts
nxt_mon_nof_sop <= nof_sop WHEN transpose_in_sosi.sync='1' ELSE i_mon_nof_sop;
nxt_mon_nof_sop <= nof_sop WHEN to_mem_src_out_i.sync='1' ELSE i_mon_nof_sop;
sync_ok_in <= '1' WHEN TO_UINT(i_mon_nof_sop) = g_nof_blk_per_sync AND TO_UINT(nof_sop) <= g_nof_blk_per_sync ELSE '0';
p_clk : PROCESS(dp_rst, dp_clk)
......@@ -365,7 +298,7 @@ BEGIN
clk => dp_clk,
-- ST sink
snk_out => OPEN,
snk_in => transpose_out_sosi,
snk_in => from_mem_snk_in,
-- ST source
src_in => OPEN,
src_out => pipeline_out_sosi
......@@ -386,7 +319,7 @@ BEGIN
PORT MAP(
rst => dp_rst,
clk => dp_clk,
snk_in => transpose_out_sosi,
snk_in => from_mem_snk_in,
-- Use incoming data to generate more data
src_in => c_dp_siso_rdy,
......@@ -394,6 +327,8 @@ BEGIN
en => '1'
);
from_mem_snk_out <= src_in_arr(0);
g_merge_out_complex : IF g_use_complex = TRUE GENERATE
gen_merge_out : PROCESS(block_gen_out_sosi, pipeline_out_sosi)
BEGIN
......
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