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Commit 8f5173f7 authored by Eric Kooistra's avatar Eric Kooistra
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Log alls BSN monitor latency results.

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applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
+ 142
− 27
View file @ 8f5173f7
......@@ -29,26 +29,68 @@
-- in the bsn_aligner_v2 at each node.
--
-- . Block diagram:
-- * tb can use one instance of tr_10Gbe to model Rx from ring and Tx to ring
-- * tb can use one instance of tr_10Gbe to model Rx from ring and Tx to ring.
-- * Ring lane serial links for ring nodes RN = 0 to c_last_rn:
--
-- tr_10gbe_ring_serial_tx_arr --> tr_10gbe_ring_serial_rx_arr after c_cable_delay
--
-- /<-------------------------------------------------------------\
-- \---> 0 ---> RN - 1 ---> RN ---> RN + 1 ---> c_last_rn --->/
-- | ^
-- tr_10gbe_ring_serial_tx_arr(RN) | | tr_10gbe_ring_serial_tx_arr(RN)
-- v |
-- |^
-- tr_10gbe_ring_serial_tx_arr(RN) || tr_10gbe_ring_serial_tx_arr(RN)
-- v|
-- tr_10Gbe
-- | ^
-- tr_10gbe_ring_rx_sosi_arr(RN) | | tr_10gbe_ring_tx_sosi_arr(RN)
-- v |
-- |^
-- tr_10gbe_ring_rx_sosi_arr(RN) || tr_10gbe_ring_tx_sosi_arr(RN)
-- v|
-- ring_lane
-- | ^
-- from_ri_sosi_arr(RN) | | to_ri_sosi_arr(RN)
-- v |
-- |^
-- from_ri_sosi_arr(RN) || to_ri_sosi_arr(RN)
-- v|
-- local_bf_sosi --> sdp_beamformer_remote --> bf_sum_sosi_arr(RN)
-- bf_sum_sosi
-- * BSN monitors:
-- RN
-- |^
-- ring_lane/ring_rx || ring_lane/ring_tx
-- FPGA_bf_ring_rx_latency_R(RN) || FPGA_bf_ring_tx_latency_R(RN)
-- ||
-- dp_bsn_align_v2 P_sum = 2 inputs ||
-- FPGA_bf_rx_align_latency_R(RN)(P_sum) ||
-- ||
-- dp_bsn_align_v2 aligned output ||
-- FPGA_bf_aligned_latency_R(RN) v|
--
-- . Latency results from SDP-ARTS HW with 16 ring nodes (GN = 64 is RN = 0)
-- - 2024-03-02T21.16.33_d601da896_lofar2_unb2b_sdp_station_full_wg
--
-- Node: bf_ring_rx bf_rx_align bf_aligned bf_ring_tx
-- _latency: _latency: _latency: _latency:
-- 64: -1 ( 1 -1 ) 2053 3114
-- 65: 4898 ( 1 3880 ) 4101 5162
-- 66: 6949 ( 1 5916 ) 6149 7210
-- 67: 8998 ( 1 7960 ) 8197 9258
-- 68: 11048 ( 1 10003 ) 10245 11306
-- 69: 13093 ( 1 12063 ) 12293 13354
-- 70: 15135 ( 1 14105 ) 14341 15402
-- 71: 17174 ( 1 16154 ) 16389 17450
-- 72: 19261 ( 1 18229 ) 18437 19498
-- 73: 21288 ( 1 20261 ) 20485 21546
-- 74: 23319 ( 1 22292 ) 22533 23594
-- 75: 25367 ( 1 24359 ) 24581 25642
-- 76: 27448 ( 1 26417 ) 26629 27690
-- 77: 29471 ( 1 28453 ) 28677 29738
-- 78: 31512 ( 1 30481 ) 30725 31786
-- 79: 33567 ( 1 32537 ) 32773 -1
--
-- Simulation latency results with this tb
-- Node: bf_ring_rx bf_rx_align bf_aligned bf_ring_tx
-- _latency: _latency: _latency: _latency:
-- 0: -1 ( 1 0 ) 2053 2075
-- 1: 3862 ( 1 3875 ) 4101 4123
-- 2: 5914 ( 1 5927 ) 6149 6171
-- 3: 7965 ( 1 7978 ) 8197 -1
--
-- Usage:
-- > as 8
-- > run -a
......@@ -69,7 +111,7 @@ use work.tb_sdp_pkg.all;
entity tb_sdp_beamformer_remote_ring is
generic (
g_nof_rn : natural := 3 -- number of nodes in the ring
g_nof_rn : natural := 4 -- number of nodes in the ring
);
end tb_sdp_beamformer_remote_ring;
......@@ -146,7 +188,7 @@ architecture tb of tb_sdp_beamformer_remote_ring is
signal tr_10gbe_ring_serial_rx_arr : std_logic_vector(c_last_rn downto 0) := (others => '0');
signal tr_10gbe_ring_serial_tx_arr : std_logic_vector(c_last_rn downto 0) := (others => '0');
-- BF ring MM points
-- BF ring MM registers
signal reg_ring_lane_info_bf_copi_arr : t_mem_copi_arr(c_last_rn downto 0) := (others => c_mem_copi_rst);
signal reg_ring_lane_info_bf_cipo_arr : t_mem_cipo_arr(c_last_rn downto 0) := (others => c_mem_cipo_rst);
signal reg_ring_lane_info_bf_copi : t_mem_copi := c_mem_copi_rst;
......@@ -169,20 +211,27 @@ architecture tb of tb_sdp_beamformer_remote_ring is
(others => c_mem_cipo_rst);
signal reg_dp_block_validate_bsn_at_sync_bf_copi : t_mem_copi := c_mem_copi_rst;
signal reg_dp_block_validate_bsn_at_sync_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
-- BF ring MM points
signal FPGA_bf_ring_nof_transport_hops_R : t_natural_arr(c_last_rn downto 0);
signal FPGA_bf_ring_rx_latency_R : t_integer_arr(c_last_rn downto 0);
signal FPGA_bf_ring_tx_latency_R : t_integer_arr(c_last_rn downto 0);
-- BSN aligner MM points
-- BSN aligner MM registers
signal reg_bsn_align_v2_bf_copi_arr : t_mem_copi_arr(c_last_rn downto 0) := (others => c_mem_copi_rst);
signal reg_bsn_align_v2_bf_cipo_arr : t_mem_cipo_arr(c_last_rn downto 0) := (others => c_mem_cipo_rst);
signal reg_bsn_align_v2_bf_copi : t_mem_copi := c_mem_copi_rst;
signal reg_bsn_align_v2_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
signal reg_bsn_monitor_v2_rx_align_bf_copi_arr : t_mem_copi_arr(c_last_rn downto 0) := (others => c_mem_copi_rst);
signal reg_bsn_monitor_v2_rx_align_bf_cipo_arr : t_mem_cipo_arr(c_last_rn downto 0) := (others => c_mem_cipo_rst);
signal reg_bsn_monitor_v2_aligned_bf_copi_arr : t_mem_copi_arr(c_last_rn downto 0) := (others => c_mem_copi_rst);
signal reg_bsn_monitor_v2_aligned_bf_cipo_arr : t_mem_cipo_arr(c_last_rn downto 0) := (others => c_mem_cipo_rst);
signal reg_bsn_monitor_v2_bf_rx_align_copi_arr : t_mem_copi_arr(c_last_rn downto 0) := (others => c_mem_copi_rst);
signal reg_bsn_monitor_v2_bf_rx_align_cipo_arr : t_mem_cipo_arr(c_last_rn downto 0) := (others => c_mem_cipo_rst);
signal reg_bsn_monitor_v2_bf_rx_align_copi : t_mem_copi := c_mem_copi_rst;
signal reg_bsn_monitor_v2_bf_rx_align_cipo : t_mem_cipo := c_mem_cipo_rst;
signal reg_bsn_monitor_v2_bf_aligned_copi_arr : t_mem_copi_arr(c_last_rn downto 0) := (others => c_mem_copi_rst);
signal reg_bsn_monitor_v2_bf_aligned_cipo_arr : t_mem_cipo_arr(c_last_rn downto 0) := (others => c_mem_cipo_rst);
signal reg_bsn_monitor_v2_bf_aligned_copi : t_mem_copi := c_mem_copi_rst;
signal reg_bsn_monitor_v2_bf_aligned_cipo : t_mem_cipo := c_mem_cipo_rst;
-- BSN aligner Monitor Points
signal FPGA_bf_rx_align_latency_R : t_integer_2arr_2(c_last_rn downto 0); -- c_sdp_P_sum = 2
signal FPGA_bf_aligned_latency_R : t_integer_arr(c_last_rn downto 0);
begin
dp_rst <= '1', '0' after c_dp_clk_period * 7;
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
......@@ -258,14 +307,38 @@ begin
-- Wait until second bf_sum_sosi.sync
proc_common_wait_until_hi_lo(dp_clk, bf_sum_sosi.sync);
proc_common_wait_until_hi_lo(dp_clk, bf_sum_sosi.sync);
-- Read FPGA_bf_ring_rx_latency_R
-- Read BSN monitors
v_span := 2**c_sdp_reg_bsn_monitor_v2_addr_w;
-- Read FPGA_bf_ring_rx_latency_R
for RN in 0 to c_last_rn LOOP
v_offset := 6 + RN * v_span;
proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_cipo, reg_bsn_monitor_v2_ring_rx_bf_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
FPGA_bf_ring_rx_latency_R(RN) <= TO_SINT(reg_bsn_monitor_v2_ring_rx_bf_cipo.rddata(c_word_w - 1 downto 0));
end loop;
-- Read FPGA_bf_rx_align_latency_R, for both c_sdp_P_sum = 2 inputs per RN
for RN in 0 to c_last_rn LOOP
for I in 0 to c_sdp_P_sum - 1 loop
v_offset := 6 + RN * c_sdp_P_sum * v_span + I * v_span;
proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_bf_rx_align_cipo, reg_bsn_monitor_v2_bf_rx_align_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
FPGA_bf_rx_align_latency_R(RN)(I) <= TO_SINT(reg_bsn_monitor_v2_bf_rx_align_cipo.rddata(c_word_w - 1 downto 0));
end loop;
end loop;
-- Read FPGA_bf_aligned_latency_R
for RN in 0 to c_last_rn LOOP
v_offset := 6 + RN * v_span;
proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_bf_aligned_cipo, reg_bsn_monitor_v2_bf_aligned_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
FPGA_bf_aligned_latency_R(RN) <= TO_SINT(reg_bsn_monitor_v2_bf_aligned_cipo.rddata(c_word_w - 1 downto 0));
end loop;
-- Read FPGA_bf_ring_tx_latency_R
for RN in 0 to c_last_rn LOOP
v_offset := 6 + RN * v_span;
proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_cipo, reg_bsn_monitor_v2_ring_tx_bf_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
FPGA_bf_ring_tx_latency_R(RN) <= TO_SINT(reg_bsn_monitor_v2_ring_tx_bf_cipo.rddata(c_word_w - 1 downto 0));
end loop;
mm_init <= '0';
......@@ -273,10 +346,16 @@ begin
proc_common_wait_until_high(dp_clk, stimuli_end);
proc_common_wait_some_cycles(dp_clk, 1000);
-- Print results
print_str("FPGA_bf_ring_rx_latency_R");
-- Print latency results
print_str("Node: bf_ring_rx bf_rx_align bf_aligned bf_ring_tx");
print_str(" _latency: _latency: _latency: _latency:");
for RN in 0 to c_last_rn loop
print_str(" RN " & int_to_str(RN) & ": " & int_to_str(FPGA_bf_ring_rx_latency_R(RN)));
print_str(int_to_str(RN) & ": " &
int_to_str(FPGA_bf_ring_rx_latency_R(RN)) & " ( " &
int_to_str(FPGA_bf_rx_align_latency_R(RN)(0)) & " " &
int_to_str(FPGA_bf_rx_align_latency_R(RN)(1)) & " ) " &
int_to_str(FPGA_bf_aligned_latency_R(RN)) & " " &
int_to_str(FPGA_bf_ring_tx_latency_R(RN)));
end Loop;
tb_end <= '1';
......@@ -405,10 +484,10 @@ begin
reg_bsn_align_copi => reg_bsn_align_v2_bf_copi_arr(RN),
reg_bsn_align_cipo => reg_bsn_align_v2_bf_cipo_arr(RN),
reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_bf_copi_arr(RN),
reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo_arr(RN),
reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_bf_copi_arr(RN),
reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_bf_cipo_arr(RN)
reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bf_rx_align_copi_arr(RN),
reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bf_rx_align_cipo_arr(RN),
reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bf_aligned_copi_arr(RN),
reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bf_aligned_cipo_arr(RN)
);
end generate; -- gen_dut
......@@ -467,6 +546,42 @@ begin
miso_arr => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr
);
u_mem_mux_reg_bsn_monitor_v2_ring_tx_bf : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_rn,
g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
)
port map (
mosi => reg_bsn_monitor_v2_ring_tx_bf_copi,
miso => reg_bsn_monitor_v2_ring_tx_bf_cipo,
mosi_arr => reg_bsn_monitor_v2_ring_tx_bf_copi_arr,
miso_arr => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr
);
u_mem_mux_reg_bsn_monitor_v2_bf_rx_align : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_rn,
g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w + ceil_log2(c_sdp_P_sum)
)
port map (
mosi => reg_bsn_monitor_v2_bf_rx_align_copi,
miso => reg_bsn_monitor_v2_bf_rx_align_cipo,
mosi_arr => reg_bsn_monitor_v2_bf_rx_align_copi_arr,
miso_arr => reg_bsn_monitor_v2_bf_rx_align_cipo_arr
);
u_mem_mux_reg_bsn_monitor_v2_bf_aligned : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_rn,
g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
)
port map (
mosi => reg_bsn_monitor_v2_bf_aligned_copi,
miso => reg_bsn_monitor_v2_bf_aligned_cipo,
mosi_arr => reg_bsn_monitor_v2_bf_aligned_copi_arr,
miso_arr => reg_bsn_monitor_v2_bf_aligned_cipo_arr
);
u_mem_mux_reg_bsn_align_v2_bf : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_rn,
......
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