Set altera_reserved_tck and altera_ts_clk as asynchronous

applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank.sdc

@@ -62,6 +62,10 @@ set_clock_groups -asynchronous -group {SA_CLK}
 set_clock_groups -asynchronous -group {SB_CLK}
 # Do not put ETH_CLK in this list, otherwise the Triple Speed Ethernet does not work
 
+set_clock_groups -asynchronous -group [get_clocks altera_ts_clk]
+
+set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]
+
 # IOPLL outputs (which have global names defined in the IP qsys settings)
 set_clock_groups -asynchronous -group [get_clocks pll_clk20]
 set_clock_groups -asynchronous -group [get_clocks pll_clk50]
@@ -88,8 +92,6 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
 #-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
 #-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
 
-
-
 # false paths added for the jesd test design
 set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}]
 set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]