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Commit 8e26de41 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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This design: 24 QSFP channels. synthesis ok

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boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+ 87
− 84
View file @ 8e26de41
......@@ -49,8 +49,8 @@ ENTITY unb2_test IS
g_factory_image : BOOLEAN := FALSE;
g_nof_streams_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
g_nof_streams_ring : NATURAL := c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
g_nof_streams_back0: NATURAL := c_unb2_board_tr_back.bus_w;
g_nof_streams_back1: NATURAL := c_unb2_board_tr_back.bus_w
g_nof_streams_back0: NATURAL := 0;--c_unb2_board_tr_back.bus_w;
g_nof_streams_back1: NATURAL := 0 --c_unb2_board_tr_back.bus_w
);
PORT (
-- GENERAL
......@@ -80,8 +80,8 @@ ENTITY unb2_test IS
BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines
-- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
......@@ -476,8 +476,8 @@ BEGIN
g_hdr_field_arr => c_hdr_field_arr,
g_nof_streams_qsfp => g_nof_streams_qsfp,
g_nof_streams_ring => g_nof_streams_ring,
g_nof_streams_back0 => g_nof_streams_back0,
g_nof_streams_back1 => g_nof_streams_back1
g_nof_streams_back0 => c_unb2_board_tr_back.bus_w,--g_nof_streams_back0,
g_nof_streams_back1 => c_unb2_board_tr_back.bus_w --g_nof_streams_back1
)
PORT MAP(
mm_rst => mm_rst,
......@@ -814,58 +814,58 @@ BEGIN
serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
);
u_tr_10GbE_back0: ENTITY unb2_board_lib.unb2_board_10gbe -- Lower Back lines
GENERIC MAP (
g_technology => g_technology,
g_sim => g_sim,
g_sim_level => 1,
g_nof_macs => g_nof_streams_back0,
g_tx_fifo_fill => c_def_10GbE_block_size,
g_tx_fifo_size => c_def_10GbE_block_size*2
)
PORT MAP (
tr_ref_clk => BCK_REF_CLK,
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mac_mosi => reg_tr_10GbE_back0_mosi,
reg_mac_miso => reg_tr_10GbE_back0_miso,
dp_rst => dp_rst,
dp_clk => dp_clk,
src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
serial_tx_arr => i_serial_10G_tx_back0_arr,
serial_rx_arr => i_serial_10G_rx_back0_arr
);
u_tr_10GbE_back1: ENTITY unb2_board_lib.unb2_board_10gbe -- Upper Back lines
GENERIC MAP (
g_technology => g_technology,
g_sim => g_sim,
g_sim_level => 1,
g_nof_macs => g_nof_streams_back1,
g_tx_fifo_fill => c_def_10GbE_block_size,
g_tx_fifo_size => c_def_10GbE_block_size*2
)
PORT MAP (
tr_ref_clk => SB_CLK,
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mac_mosi => reg_tr_10GbE_back1_mosi,
reg_mac_miso => reg_tr_10GbE_back1_miso,
dp_rst => dp_rst,
dp_clk => dp_clk,
src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
serial_tx_arr => i_serial_10G_tx_back1_arr,
serial_rx_arr => i_serial_10G_rx_back1_arr
);
-- u_tr_10GbE_back0: ENTITY unb2_board_lib.unb2_board_10gbe -- Lower Back lines
-- GENERIC MAP (
-- g_technology => g_technology,
-- g_sim => g_sim,
-- g_sim_level => 1,
-- g_nof_macs => g_nof_streams_back0,
-- g_tx_fifo_fill => c_def_10GbE_block_size,
-- g_tx_fifo_size => c_def_10GbE_block_size*2
-- )
-- PORT MAP (
-- tr_ref_clk => BCK_REF_CLK,
-- mm_rst => mm_rst,
-- mm_clk => mm_clk,
-- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
-- reg_mac_miso => reg_tr_10GbE_back0_miso,
-- dp_rst => dp_rst,
-- dp_clk => dp_clk,
-- src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
-- src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
-- snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
-- snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
--
-- serial_tx_arr => i_serial_10G_tx_back0_arr,
-- serial_rx_arr => i_serial_10G_rx_back0_arr
-- );
-- u_tr_10GbE_back1: ENTITY unb2_board_lib.unb2_board_10gbe -- Upper Back lines
-- GENERIC MAP (
-- g_technology => g_technology,
-- g_sim => g_sim,
-- g_sim_level => 1,
-- g_nof_macs => g_nof_streams_back1,
-- g_tx_fifo_fill => c_def_10GbE_block_size,
-- g_tx_fifo_size => c_def_10GbE_block_size*2
-- )
-- PORT MAP (
-- tr_ref_clk => SB_CLK,
-- mm_rst => mm_rst,
-- mm_clk => mm_clk,
-- reg_mac_mosi => reg_tr_10GbE_back1_mosi,
-- reg_mac_miso => reg_tr_10GbE_back1_miso,
-- dp_rst => dp_rst,
-- dp_clk => dp_clk,
--
-- src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
-- src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
-- snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
-- snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
--
-- serial_tx_arr => i_serial_10G_tx_back1_arr,
-- serial_rx_arr => i_serial_10G_rx_back1_arr
-- );
......@@ -938,34 +938,37 @@ BEGIN
);
gen_back0_wires: FOR i IN 0 TO g_nof_streams_back0-1 GENERATE
serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
END GENERATE;
gen_back1_wires: FOR i IN 0 TO g_nof_streams_back1-1 GENERATE
serial_10G_tx_back_arr(i+g_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+g_nof_streams_back0);
END GENERATE;
-- gen_back0_wires: FOR i IN 0 TO g_nof_streams_back0-1 GENERATE
-- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
-- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
-- END GENERATE;
-- gen_back1_wires: FOR i IN 0 TO g_nof_streams_back1-1 GENERATE
-- serial_10G_tx_back_arr(i+g_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
-- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+g_nof_streams_back0);
-- END GENERATE;
--
-- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
-- GENERIC MAP (
-- g_nof_back_bus => g_nof_back_bus
-- )
-- PORT MAP (
-- serial_tx_arr => serial_10G_tx_back_arr,
-- serial_rx_arr => serial_10G_rx_back_arr,
--
-- -- Serial I/O
-- -- back transceivers
-- BCK_RX(0) => BCK_RX(g_nof_streams_back0-1 downto 0),
-- BCK_TX(0) => BCK_TX(g_nof_streams_back0-1 downto 0),
-- BCK_RX(1) => BCK_RX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0),
-- BCK_TX(1) => BCK_TX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0),
--
-- BCK_SDA => BCK_SDA,
-- BCK_SCL => BCK_SCL,
-- BCK_ERR => BCK_ERR
-- );
u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
GENERIC MAP (
g_nof_back_bus => g_nof_back_bus
)
PORT MAP (
serial_tx_arr => serial_10G_tx_back_arr,
serial_rx_arr => serial_10G_rx_back_arr,
-- Serial I/O
-- back transceivers
BCK_RX(0) => BCK_RX(g_nof_streams_back0-1 downto 0),
BCK_TX(0) => BCK_TX(g_nof_streams_back0-1 downto 0),
BCK_RX(1) => BCK_RX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0),
BCK_TX(1) => BCK_TX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0),
BCK_SDA => BCK_SDA,
BCK_SCL => BCK_SCL,
BCK_ERR => BCK_ERR
);
--
-- u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
-- GENERIC MAP (
......
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