processed review comments

libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd

 -------------------------------------------------------------------------------
 --
--- Copyright 2022
+-- Copyright 2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
@@ -17,6 +17,17 @@
 -- limitations under the License.
 --
 -------------------------------------------------------------------------------
+-- Author: R. van der Walle
+-- Purpose: Provide AXI4-Stream and AXI4-Lite interface for eth_tester.vhd such
+--          that it can be used to create a Vivado IP block.
+-- Description: 
+-- . The eth_tester_axi4_wrapper uses axi4_stream_dp_bridge to convert the dp
+--   sosi/siso interfaces of the eth_tester into AXI4-Stream interfaces.
+--   Similarly, axi4_lite_mm_bridge is used to convert the mem copi/cipo 
+--   interfaces into AXI4_Lite interfaces.
+-- . In order for this component to be suitable as a Vivado IP, the ports are
+--   exclusively STD_LOGIC(_VECTOR) where the widths are hard-coded as demanded
+--   by the Vivado IP creator (only supports VHDL-93).
 
 LIBRARY IEEE, common_lib, dp_lib, diag_lib, axi4_lib;
 USE IEEE.std_logic_1164.ALL;

libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd

@@ -50,11 +50,9 @@ ENTITY ip_ultrascale_fifo_dc IS
   );
 END ip_ultrascale_fifo_dc;
 
-
 ARCHITECTURE SYN OF ip_ultrascale_fifo_dc IS
 
 BEGIN
-
    -- xpm_fifo_async: Asynchronous FIFO
    -- Xilinx Parameterized Macro, version 2022.1
 
@@ -172,9 +170,7 @@ BEGIN
       wr_en => wrreq                  -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
                                       -- signal causes data (on din) to be written to the FIFO. Must be held
                                       -- active-low when rst or wr_rst_busy is active high.
-
    );
 
    -- End of xpm_fifo_async_inst instantiation
-
 END SYN;

libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd

@@ -51,14 +51,9 @@ ENTITY ip_ultrascale_fifo_dc_mixed_widths IS
   );
 END ip_ultrascale_fifo_dc_mixed_widths;
 
-
 ARCHITECTURE SYN OF ip_ultrascale_fifo_dc_mixed_widths IS
-
     
 BEGIN
-
-
-
    -- xpm_fifo_async: Asynchronous FIFO
    -- Xilinx Parameterized Macro, version 2022.1
 
@@ -176,10 +171,8 @@ BEGIN
       wr_en => wrreq                  -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
                                       -- signal causes data (on din) to be written to the FIFO. Must be held
                                       -- active-low when rst or wr_rst_busy is active high.
-
    );
 
    -- End of xpm_fifo_async_inst instantiation
 
-
 END SYN;

libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd

@@ -48,7 +48,6 @@ ENTITY ip_ultrascale_fifo_sc IS
   );
 END ip_ultrascale_fifo_sc;
 
-
 ARCHITECTURE SYN OF ip_ultrascale_fifo_sc IS
 
 BEGIN
@@ -165,7 +164,6 @@ BEGIN
       wr_en => wrreq                  -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
                                       -- signal causes data (on din) to be written to the FIFO. Must be held
                                       -- active-low when rst or wr_rst_busy is active high.
-
    );
 
    -- End of xpm_fifo_async_inst instantiation