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Commit 8c37123d authored by Zanting's avatar Zanting
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Replaced io_ddr, blockgen and data buffer with io_ddr_diag block.

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boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
+ 45
− 117
View file @ 8c37123d
......@@ -95,7 +95,7 @@ ARCHITECTURE str OF node_unb1_ddr3 IS
CONSTANT c_data_w : NATURAL := g_st_dat_w;
CONSTANT c_wr_fifo_depth : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
CONSTANT c_rd_fifo_depth : NATURAL := 1024; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
CONSTANT c_use_bg : BOOLEAN := FALSE;
CONSTANT c_use_tx_seq : BOOLEAN := TRUE;
......@@ -114,27 +114,34 @@ ARCHITECTURE str OF node_unb1_ddr3 IS
BEGIN
------------------------------------------------------------------------------
-- DDR3 MODULE 0, MB_I
------------------------------------------------------------------------------
u_mms_ddr3 : ENTITY io_ddr_lib.mms_io_ddr
u_mms_io_ddr_diag : ENTITY io_ddr_lib.mms_io_ddr_diag
GENERIC MAP(
g_technology => g_technology, --: NATURAL := c_tech_select_default;
g_tech_ddr => g_tech_ddr, --: t_c_tech_ddr;
g_cross_domain_dvr_ctlr => FALSE, --: BOOLEAN := TRUE;
g_wr_data_w => c_wr_data_w,
g_wr_fifo_depth => c_wr_fifo_depth,
g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => c_rd_data_w,
g_wr_flush_mode => "VAL",
g_wr_flush_use_channel => FALSE,
g_wr_flush_start_channel => 0,
g_wr_flush_nof_channels => 1
-- System
g_technology => g_technology,
g_dp_data_w => g_st_dat_w,
g_dp_seq_dat_w => c_seq_dat_w,
g_dp_fifo_depth => c_rd_fifo_depth,
-- IO_DDR
g_io_tech_ddr => g_tech_ddr,
-- DIAG data buffer
g_db_use_db => c_use_db,
g_db_buf_nof_data => c_buf_nof_data
)
PORT MAP (
PORT MAP(
---------------------------------------------------------------------------
-- System
---------------------------------------------------------------------------
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_clk,
dp_clk => dp_rst,
---------------------------------------------------------------------------
-- IO_DDR
---------------------------------------------------------------------------
-- DDR reference clock
ctlr_ref_clk => ddr_ref_clk,
ctlr_ref_rst => ddr_ref_rst,
ctlr_ref_clk => ddr_ref_clk,
ctlr_ref_rst => ddr_ref_rst,
-- DDR controller clock domain
ctlr_clk_out => ddr_out_clk,
......@@ -143,121 +150,42 @@ BEGIN
ctlr_clk_in => dp_clk,
ctlr_rst_in => dp_rst,
-- MM clock + reset
mm_rst => mm_rst,
mm_clk => mm_clk,
-- MM interface
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
dvr_clk => dp_clk,
dvr_rst => dp_rst,
-- Write FIFO clock domain
wr_clk => dp_clk,
wr_rst => dp_rst,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
wr_fifo_usedw => OPEN,
wr_sosi => out_sosi_arr(0),
wr_siso => out_siso_arr(0),
-- Read FIFO clock domain
rd_clk => dp_clk,
rd_rst => dp_rst,
rd_fifo_usedw => OPEN,
rd_sosi => in_sosi_arr(0),
rd_siso => in_siso_arr(0),
-- DDR3 pass on termination control from master to slave controller
term_ctrl_out => OPEN,
term_ctrl_in => OPEN,
-- DDR3 PHY external interface
phy3_in => MB_I_in,
phy3_io => MB_I_io,
phy3_ou => MB_I_ou
);
phy3_ou => MB_I_ou,
-----------------------------------------------------------------------------
-- Block Generator
-----------------------------------------------------------------------------
u_mms_diag_block_gen: ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP(
-- Generate configurations
g_use_usr_input => FALSE,
g_use_bg => c_use_bg,
g_use_tx_seq => c_use_tx_seq,
-- General
g_nof_streams => c_nof_streams,
-- BG settings
g_use_bg_buffer_ram => TRUE,
g_buf_dat_w => 32,
g_buf_addr_w => 7, -- Waveform buffer size 2**g_buf_addr_w nof samples
g_file_index_arr => array_init(0, 128, 1), -- default use the instance index as file index 0, 1, 2, 3, 4 ...
g_file_name_prefix => "data/bf_in_data", -- Path to the hex files that contain the initial data for the memories. The sequence number and ".hex" are added within the entity.
g_diag_block_gen_rst => c_diag_block_gen_rst,
-- User input multiplexer option
g_usr_bypass_xonoff => FALSE,
-- Tx_seq
g_seq_dat_w => c_seq_dat_w
)
PORT MAP(
-- System
mm_rst => mm_rst, -- reset synchronous with mm_clk
mm_clk => mm_clk, -- memory-mapped bus clock
dp_rst => dp_rst, -- reset synchronous with st_clk
dp_clk => dp_clk, -- streaming clock domain clock
en_sync => en_sync, -- block generator enable sync pulse in ST dp_clk domain
---------------------------------------------------------------------------
-- DIAG Tx seq
---------------------------------------------------------------------------
-- MM interface
reg_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi, -- BG control register (one for all streams)
reg_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
ram_bg_data_mosi => ram_diag_bg_data_mosi, -- BG buffer RAM (one per stream)
ram_bg_data_miso => ram_diag_bg_data_miso,
reg_tx_seq_mosi => reg_diag_tx_seq_mosi, -- Tx seq control (one per stream because c_reg_tx_seq_broadcast=FALSE)
reg_tx_seq_miso => reg_diag_tx_seq_miso,
-- ST interface
out_siso_arr => out_siso_arr, -- Default xon='1'
out_sosi_arr => out_sosi_arr -- Output SOSI that contains the waveform data
);
reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
reg_tx_seq_miso => reg_diag_tx_seq_miso,
-----------------------------------------------------------------------------
-- Data Buffer
-----------------------------------------------------------------------------
u_mms_diag_data_buffer: ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP(
-- Generate configurations
g_use_db => c_use_db,
g_use_rx_seq => c_use_rx_seq,
-- General
g_nof_streams => c_nof_streams,
-- DB settings
g_data_w => c_data_w,
g_buf_nof_data => c_buf_nof_data,
-- Rx_seq
g_seq_dat_w => c_seq_dat_w
)
PORT MAP(
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
---------------------------------------------------------------------------
-- DIAG rx seq with optional data buffer
---------------------------------------------------------------------------
-- MM interface
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
reg_rx_seq_miso => reg_diag_rx_seq_miso,
-- ST interface
in_sync => in_sosi_arr(0).sync,
in_sosi_arr => in_sosi_arr
reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
reg_rx_seq_miso => reg_diag_rx_seq_miso
);
END str;
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