Skip to content
Snippets Groups Projects
Commit 8bb0912d authored by Pepping's avatar Pepping
Browse files

Added entry for reg_dp_xonoff_output

parent b9c14966
Branches
No related tags found
No related merge requests found
Show whitespace changes
Inline Side-by-side
applications/apertif/designs/apertif_unb1_correlator/src/vhdl/mmm_apertif_unb1_correlator.vhd
+ 26
− 4
View file @ 8bb0912d
...@@ -108,7 +108,9 @@ ...@@ -108,7 +108,9 @@
-- reg_diag_bg_proc_mosi => reg_diag_bg_proc_mosi, -- reg_diag_bg_proc_mosi => reg_diag_bg_proc_mosi,
-- reg_diag_bg_proc_miso => reg_diag_bg_proc_miso, -- reg_diag_bg_proc_miso => reg_diag_bg_proc_miso,
-- ram_diag_bg_proc_mosi => ram_diag_bg_proc_mosi, -- ram_diag_bg_proc_mosi => ram_diag_bg_proc_mosi,
-- ram_diag_bg_proc_miso => ram_diag_bg_proc_miso -- ram_diag_bg_proc_miso => ram_diag_bg_proc_miso,
-- reg_dp_xonoff_output_mosi => reg_dp_xonoff_output_mosi,
-- reg_dp_xonoff_output_miso => reg_dp_xonoff_output_miso
-- ); -- );
-- --
-- SIGNAL reg_wdi_mosi : t_mem_mosi; -- SIGNAL reg_wdi_mosi : t_mem_mosi;
...@@ -189,6 +191,8 @@ ...@@ -189,6 +191,8 @@
-- SIGNAL reg_diag_bg_proc_miso : t_mem_miso; -- SIGNAL reg_diag_bg_proc_miso : t_mem_miso;
-- SIGNAL ram_diag_bg_proc_mosi : t_mem_mosi; -- SIGNAL ram_diag_bg_proc_mosi : t_mem_mosi;
-- SIGNAL ram_diag_bg_proc_miso : t_mem_miso; -- SIGNAL ram_diag_bg_proc_miso : t_mem_miso;
-- SIGNAL reg_dp_xonoff_output_mosi : t_mem_mosi;
-- SIGNAL reg_dp_xonoff_output_miso : t_mem_miso;
-- --
LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib; LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
...@@ -298,7 +302,9 @@ ENTITY mmm_apertif_unb1_correlator IS ...@@ -298,7 +302,9 @@ ENTITY mmm_apertif_unb1_correlator IS
reg_diag_bg_proc_mosi : OUT t_mem_mosi; reg_diag_bg_proc_mosi : OUT t_mem_mosi;
reg_diag_bg_proc_miso : IN t_mem_miso := c_mem_miso_rst; reg_diag_bg_proc_miso : IN t_mem_miso := c_mem_miso_rst;
ram_diag_bg_proc_mosi : OUT t_mem_mosi; ram_diag_bg_proc_mosi : OUT t_mem_mosi;
ram_diag_bg_proc_miso : IN t_mem_miso := c_mem_miso_rst ram_diag_bg_proc_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_xonoff_output_mosi : OUT t_mem_mosi;
reg_dp_xonoff_output_miso : IN t_mem_miso := c_mem_miso_rst
); );
END ENTITY mmm_apertif_unb1_correlator; END ENTITY mmm_apertif_unb1_correlator;
...@@ -401,7 +407,9 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS ...@@ -401,7 +407,9 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
pio_system_info_write_export : out std_logic; pio_system_info_write_export : out std_logic;
reg_tr_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); reg_tr_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
ram_fil_coefs_address_export : out std_logic_vector(8 downto 0); ram_fil_coefs_address_export : out std_logic_vector(8 downto 0);
reg_dp_xonoff_output_address_export : out std_logic;
reg_diag_bg_input_clk_export : out std_logic; reg_diag_bg_input_clk_export : out std_logic;
reg_dp_xonoff_output_reset_export : out std_logic;
rom_system_info_read_export : out std_logic; rom_system_info_read_export : out std_logic;
reg_diag_data_buffer_proc_address_export : out std_logic; reg_diag_data_buffer_proc_address_export : out std_logic;
reg_diag_data_buffer_mesh_read_export : out std_logic; reg_diag_data_buffer_mesh_read_export : out std_logic;
...@@ -458,6 +466,7 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS ...@@ -458,6 +466,7 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
rom_system_info_address_export : out std_logic_vector(9 downto 0); rom_system_info_address_export : out std_logic_vector(9 downto 0);
reg_diag_bg_mesh_writedata_export : out std_logic_vector(31 downto 0); reg_diag_bg_mesh_writedata_export : out std_logic_vector(31 downto 0);
ram_diag_data_buffer_mesh_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); ram_diag_data_buffer_mesh_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_dp_xonoff_output_write_export : out std_logic;
reg_dp_fifo_fill_clk_export : out std_logic; reg_dp_fifo_fill_clk_export : out std_logic;
ram_diag_data_buffer_input_pre_address_export : out std_logic_vector(16 downto 0); ram_diag_data_buffer_input_pre_address_export : out std_logic_vector(16 downto 0);
reg_mdio_0_address_export : out std_logic_vector(2 downto 0); reg_mdio_0_address_export : out std_logic_vector(2 downto 0);
...@@ -470,6 +479,8 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS ...@@ -470,6 +479,8 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
reg_diag_bg_proc_address_export : out std_logic_vector(2 downto 0); reg_diag_bg_proc_address_export : out std_logic_vector(2 downto 0);
ram_diag_data_buffer_input_pre_read_export : out std_logic; ram_diag_data_buffer_input_pre_read_export : out std_logic;
reg_diagnostics_write_export : out std_logic; reg_diagnostics_write_export : out std_logic;
reg_dp_xonoff_output_read_export : out std_logic;
reg_dp_xonoff_output_clk_export : out std_logic;
ram_diag_bg_input_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); ram_diag_bg_input_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
pio_pps_address_export : out std_logic; pio_pps_address_export : out std_logic;
pio_pps_reset_export : out std_logic; pio_pps_reset_export : out std_logic;
...@@ -521,9 +532,9 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS ...@@ -521,9 +532,9 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
reg_dp_offload_tx_hdr_dat_reset_export : out std_logic; reg_dp_offload_tx_hdr_dat_reset_export : out std_logic;
reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(5 downto 0); reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(5 downto 0);
reg_dp_fifo_fill_address_export : out std_logic_vector(4 downto 0); reg_dp_fifo_fill_address_export : out std_logic_vector(4 downto 0);
reg_dp_fifo_fill_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_mdio_2_read_export : out std_logic;
reg_tr_nonbonded_reset_export : out std_logic; reg_tr_nonbonded_reset_export : out std_logic;
reg_mdio_2_read_export : out std_logic;
reg_dp_fifo_fill_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_mdio_1_writedata_export : out std_logic_vector(31 downto 0); reg_mdio_1_writedata_export : out std_logic_vector(31 downto 0);
reg_diag_bg_mesh_write_export : out std_logic; reg_diag_bg_mesh_write_export : out std_logic;
reg_mdio_2_reset_export : out std_logic; reg_mdio_2_reset_export : out std_logic;
...@@ -539,6 +550,7 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS ...@@ -539,6 +550,7 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
rom_system_info_write_export : out std_logic; rom_system_info_write_export : out std_logic;
ram_diag_data_buffer_mesh_writedata_export : out std_logic_vector(31 downto 0); ram_diag_data_buffer_mesh_writedata_export : out std_logic_vector(31 downto 0);
reg_dp_offload_tx_hdr_dat_clk_export : out std_logic; reg_dp_offload_tx_hdr_dat_clk_export : out std_logic;
reg_dp_xonoff_output_writedata_export : out std_logic_vector(31 downto 0);
reg_diag_data_buffer_proc_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); reg_diag_data_buffer_proc_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_mdio_2_clk_export : out std_logic; reg_mdio_2_clk_export : out std_logic;
reg_dp_bsn_align_input_address_export : out std_logic_vector(1 downto 0); reg_dp_bsn_align_input_address_export : out std_logic_vector(1 downto 0);
...@@ -567,6 +579,7 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS ...@@ -567,6 +579,7 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
ram_diag_data_buffer_mesh_address_export : out std_logic_vector(5 downto 0); ram_diag_data_buffer_mesh_address_export : out std_logic_vector(5 downto 0);
reg_tr_10gbe_reset_export : out std_logic; reg_tr_10gbe_reset_export : out std_logic;
ram_diag_data_buffer_input_post_address_export : out std_logic_vector(16 downto 0); ram_diag_data_buffer_input_post_address_export : out std_logic_vector(16 downto 0);
reg_dp_fifo_fill_reset_export : out std_logic;
reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0);
out_port_from_the_pio_wdi : out std_logic; out_port_from_the_pio_wdi : out std_logic;
reg_diag_data_buffer_mesh_write_export : out std_logic; reg_diag_data_buffer_mesh_write_export : out std_logic;
...@@ -683,6 +696,8 @@ BEGIN ...@@ -683,6 +696,8 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_diag_bg_proc_mosi, reg_diag_bg_proc_miso ); PORT MAP(mm_rst, mm_clk, reg_diag_bg_proc_mosi, reg_diag_bg_proc_miso );
u_mm_file_ram_diag_bg_proc : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_PROC") u_mm_file_ram_diag_bg_proc : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_PROC")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_proc_mosi, ram_diag_bg_proc_miso ); PORT MAP(mm_rst, mm_clk, ram_diag_bg_proc_mosi, ram_diag_bg_proc_miso );
u_mm_file_reg_dp_xonoff_output : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_OUTPUT")
PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_output_mosi, reg_dp_xonoff_output_miso );
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS -- 1GbE setup sequence normally performed by unb_os@NIOS
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
...@@ -905,6 +920,7 @@ BEGIN ...@@ -905,6 +920,7 @@ BEGIN
reg_dp_fifo_fill_clk_export => OPEN, reg_dp_fifo_fill_clk_export => OPEN,
reg_dp_fifo_fill_read_export => reg_dp_fifo_fill_mosi.rd, reg_dp_fifo_fill_read_export => reg_dp_fifo_fill_mosi.rd,
reg_dp_fifo_fill_readdata_export => reg_dp_fifo_fill_miso.rddata(c_word_w-1 DOWNTO 0), reg_dp_fifo_fill_readdata_export => reg_dp_fifo_fill_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dp_fifo_fill_reset_export => OPEN,
reg_dp_fifo_fill_write_export => reg_dp_fifo_fill_mosi.wr, reg_dp_fifo_fill_write_export => reg_dp_fifo_fill_mosi.wr,
reg_dp_fifo_fill_writedata_export => reg_dp_fifo_fill_mosi.wrdata(c_word_w-1 DOWNTO 0), reg_dp_fifo_fill_writedata_export => reg_dp_fifo_fill_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(6 DOWNTO 0), reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(6 DOWNTO 0),
...@@ -921,6 +937,12 @@ BEGIN ...@@ -921,6 +937,12 @@ BEGIN
reg_dp_offload_tx_hdr_dat_reset_export => OPEN, reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr, reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr,
reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0), reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_xonoff_output_address_export => reg_dp_xonoff_output_mosi.address(0),
reg_dp_xonoff_output_clk_export => OPEN,
reg_dp_xonoff_output_read_export => reg_dp_xonoff_output_mosi.rd,
reg_dp_xonoff_output_reset_export => OPEN,
reg_dp_xonoff_output_write_export => reg_dp_xonoff_output_mosi.wr,
reg_dp_xonoff_output_writedata_export => reg_dp_xonoff_output_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_mdio_0_address_export => reg_mdio_0_mosi.address(2 DOWNTO 0), reg_mdio_0_address_export => reg_mdio_0_mosi.address(2 DOWNTO 0),
reg_mdio_0_clk_export => OPEN, reg_mdio_0_clk_export => OPEN,
reg_mdio_0_read_export => reg_mdio_0_mosi.rd, reg_mdio_0_read_export => reg_mdio_0_mosi.rd,
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment