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Commit 8ba771b9 authored by Eric Kooistra's avatar Eric Kooistra
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Merge branch 'master' of git.astron.nl:desp/hdl

parents 73e84c22 8d6e6a3c
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Pipeline #24161 passed
Stage: simulation
Stage: synthesis
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applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
+ 50
− 47
View file @ 8ba771b9
......@@ -52,18 +52,23 @@ USE work.lofar2_unb2b_ring_pkg.ALL;
ENTITY tb_lofar2_unb2b_ring IS
GENERIC (
g_multi_tb : BOOLEAN := FALSE;
g_unb_nr : NATURAL := 0;
g_design_name : STRING := "lofar2_unb2b_ring_full";
g_nof_rn : NATURAL := 3;
g_nof_block_per_sync : NATURAL := 3;
g_access_scheme : INTEGER RANGE 1 TO 3 := 1
);
PORT (
tb_end : OUT STD_LOGIC := '0' -- For multi tb
);
END tb_lofar2_unb2b_ring;
ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_node_nr : NATURAL := 0;
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(g_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(0, c_unb2b_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
......@@ -82,11 +87,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
CONSTANT c_block_period : NATURAL := 1024;
CONSTANT c_blocksize : NATURAL := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size;
CONSTANT c_gapsize : NATURAL := c_block_period - c_blocksize;
CONSTANT c_nof_block_per_sync : NATURAL := 3;
CONSTANT c_sync_timeout : NATURAL := c_block_period * c_nof_block_per_sync + 10; -- +10 for extra slack
CONSTANT c_exp_bsn_at_sync : NATURAL := c_nof_block_per_sync;
CONSTANT c_exp_nof_sop : NATURAL := c_nof_block_per_sync;
CONSTANT c_exp_nof_valid : NATURAL := c_nof_block_per_sync * c_blocksize;
CONSTANT c_sync_timeout : NATURAL := c_block_period * g_nof_block_per_sync + 10; -- +10 for extra slack
CONSTANT c_exp_bsn_at_sync : NATURAL := g_nof_block_per_sync;
CONSTANT c_exp_nof_sop : NATURAL := g_nof_block_per_sync;
CONSTANT c_exp_nof_valid : NATURAL := g_nof_block_per_sync * c_blocksize;
-- MM
......@@ -100,7 +104,6 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
CONSTANT c_mm_file_reg_bsn_monitor_v2_ring_tx : STRING := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_RING_TX";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL tb_clk : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
......@@ -161,14 +164,14 @@ BEGIN
------------------------------------------------------------------------------
-- DUTs
------------------------------------------------------------------------------
gen_dut : FOR I IN 0 TO g_nof_rn -1 GENERATE
gen_dut : FOR RN IN 0 TO g_nof_rn -1 GENERATE
u_lofar_unb2b_ring : ENTITY work.lofar2_unb2b_ring
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => "",
g_sim => c_sim,
g_sim_unb_nr => g_unb_nr,
g_sim_node_nr => I,
g_sim_unb_nr => g_unb_nr + (RN / c_quad),
g_sim_node_nr => RN MOD c_quad,
g_sim_sync_timeout => c_sync_timeout
)
PORT MAP (
......@@ -181,7 +184,7 @@ BEGIN
-- Others
VERSION => c_version,
ID => ( TO_UVEC(g_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(I, c_unb2b_board_nof_chip_w) ),
ID => ( TO_UVEC(RN / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC(RN MOD c_quad, c_unb2c_board_nof_chip_w) ),
TESTIO => open,
-- I2C Interface to Sensors
......@@ -200,14 +203,14 @@ BEGIN
-- Transceiver clocks
SA_CLK => SA_CLK,
-- front transceivers
QSFP_0_RX => i_QSFP_0_RX(I),
QSFP_0_TX => i_QSFP_0_TX(I),
QSFP_0_RX => i_QSFP_0_RX(RN),
QSFP_0_TX => i_QSFP_0_TX(RN),
-- ring transceivers
RING_0_RX => i_RING_0_RX(I),
RING_0_TX => i_RING_0_TX(I),
RING_1_RX => i_RING_1_RX(I),
RING_1_TX => i_RING_1_TX(I),
RING_0_RX => i_RING_0_RX(RN),
RING_0_TX => i_RING_0_TX(RN),
RING_1_RX => i_RING_1_RX(RN),
RING_1_TX => i_RING_1_TX(RN),
-- LEDs
QSFP_LED => open
......@@ -240,8 +243,8 @@ BEGIN
-- Write ring configuration to all nodes.
FOR RN IN 0 TO g_nof_rn-1 LOOP
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_RING_INFO", 2, g_nof_rn, tb_clk); -- N_rn
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_RING_INFO", 3, 0, tb_clk); -- O_rn
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_INFO", 2, g_nof_rn, tb_clk); -- N_rn
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_INFO", 3, 0, tb_clk); -- O_rn
END LOOP;
-- Start node specific settings
......@@ -249,8 +252,8 @@ BEGIN
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk); -- use_ring_to_next_rn = 0
-- End node specific settings
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, g_nof_rn-1) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, g_nof_rn-1) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn-1) / c_quad), (g_nof_rn-1) MOD c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn-1) / c_quad), (g_nof_rn-1) MOD c_quad) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
----------------------------------------------------------------------------
-- Access scheme 1. A source RN creates the packets and sends them along the ring.
......@@ -272,11 +275,11 @@ BEGIN
FOR RN IN 0 TO g_nof_rn-1 LOOP
FOR I IN 0 TO c_nof_lanes-1 LOOP
-- Select both local and remote input on all nodes on all lanes.
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DP_XONOFF_LANE", I*2, 1, tb_clk); -- Enable input from lane
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DP_XONOFF_LOCAL", I*2, 1, tb_clk); -- Enable local input
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DP_XONOFF_LANE", I*2, 1, tb_clk); -- Enable input from lane
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DP_XONOFF_LOCAL", I*2, 1, tb_clk); -- Enable local input
-- Set transport_nof_hops to N_rn-1 on all nodes.
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_RING_LANE_INFO", I*2+1, g_nof_rn-1, tb_clk);
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_LANE_INFO", I*2+1, g_nof_rn-1, tb_clk);
END LOOP;
END LOOP;
END IF;
......@@ -284,10 +287,10 @@ BEGIN
-- Enable BG on all nodes (for bs_sosi)
----------------------------------------------------------------------------
FOR RN IN 0 TO g_nof_rn-1 LOOP
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 1, c_blocksize, tb_clk); -- samples per packet
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 2, c_nof_block_per_sync, tb_clk); -- blocks per sync
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 3, c_gapsize, tb_clk); -- gapsize
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 0, 3, tb_clk); -- enable at sync
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DIAG_BG", 1, c_blocksize, tb_clk); -- samples per packet
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DIAG_BG", 2, g_nof_block_per_sync, tb_clk); -- blocks per sync
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DIAG_BG", 3, c_gapsize, tb_clk); -- gapsize
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DIAG_BG", 0, 3, tb_clk); -- enable at sync
END LOOP;
----------------------------------------------------------------------------
-- Verify Access scheme 1 by reading rx / tx monitors on source RN
......@@ -323,7 +326,7 @@ BEGIN
----------------------------------------------------------------------------
ELSE
-- Wait for bsn monitor to have received a sync period.
mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr, g_nof_rn-1) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn-1) / c_quad), (g_nof_rn-1) MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
"SIGNED", rd_data, ">", 0, -- this is the wait until condition
1 us, tb_clk); -- read every 1 us
......@@ -332,33 +335,33 @@ BEGIN
FOR J IN 0 TO g_nof_rn-1 LOOP -- bsn_monitor index
-- No packets transmitted from next RN (this_rn + 1 for even lanes, this_rn - 1 for odd lanes) as this RN should have removed it from the ring.
IF (I MOD 2 = 0 AND (RN + 1) MOD g_nof_rn = J) OR (I MOD 2 = 1 AND (RN + g_nof_rn-1) MOD g_nof_rn = J) THEN
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
ASSERT rd_data(2) = '1' REPORT "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
ELSE
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
ASSERT rd_data(2) = '0' REPORT "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
ASSERT TO_UINT(rd_data) = c_exp_nof_sop REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
ASSERT TO_UINT(rd_data) = c_exp_nof_valid REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+5, rd_data, tb_clk); --nof_err
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+5, rd_data, tb_clk); --nof_err
ASSERT TO_UINT(rd_data) = 0 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
END IF;
IF RN = J THEN -- No packets received from itself as the previous RN should have removed it from the ring.
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
ASSERT rd_data(2) = '1' REPORT "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
ELSE
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
ASSERT rd_data(2) = '0' REPORT "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
ASSERT TO_UINT(rd_data) = c_exp_nof_sop REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
ASSERT TO_UINT(rd_data) = c_exp_nof_valid REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+5, rd_data, tb_clk); --nof_err
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+5, rd_data, tb_clk); --nof_err
ASSERT TO_UINT(rd_data) = 0 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
END IF;
END LOOP;
......@@ -371,7 +374,7 @@ BEGIN
---------------------------------------------------------------------------
sim_done <= '1';
proc_common_wait_some_cycles(ext_clk, 100);
proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, tb_end);
WAIT;
END PROCESS;
......
applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
+ 25
− 11
View file @ 8ba771b9
......@@ -27,24 +27,38 @@
-- > run -all
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.common_pkg.ALL;
ENTITY tb_tb_lofar2_unb2b_ring IS
END tb_tb_lofar2_unb2b_ring;
ARCHITECTURE tb OF tb_tb_lofar2_unb2b_ring IS
CONSTANT c_nof_rn : NATURAL := 3;
SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
CONSTANT c_nof_tb : NATURAL := 5;
SIGNAL tb_end : STD_LOGIC_VECTOR(c_nof_tb-1 DOWNTO 0) := (OTHERS => '0'); -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
SIGNAL tb_end_and : STD_LOGIC;
BEGIN
-- g_unb_nr : NATURAL := 0;
-- g_design_name : STRING := "lofar2_unb2b_ring_full";
-- g_nof_rn : NATURAL := 3;
-- g_access_scheme : INTEGER RANGE 1 TO 3 := 1
-- g_multi_tb : BOOLEAN := FALSE;
-- g_unb_nr : NATURAL := 4;
-- g_design_name : STRING := "lofar2_unb2c_ring_one";
-- g_nof_rn : NATURAL := 16;
-- g_nof_block_per_sync : NATURAL := 32;
-- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
-- using different g_unb_nr to avoid MM file clashing.
u_one_1 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(0, "lofar2_unb2b_ring_one", c_nof_rn, 1); -- access scheme 1.
u_one_2_3 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(1, "lofar2_unb2b_ring_one", c_nof_rn, 2); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_full_1 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(2, "lofar2_unb2b_ring_full", c_nof_rn, 1); -- access scheme 1.
u_full_2_3 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(3, "lofar2_unb2b_ring_full", c_nof_rn, 2); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_one_1 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(TRUE, 0, "lofar2_unb2b_ring_one", c_nof_rn, 3, 1) PORT MAP(tb_end(0)); -- access scheme 1.
u_one_2_3 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(TRUE, 1, "lofar2_unb2b_ring_one", c_nof_rn, 3, 2) PORT MAP(tb_end(1)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_full_1 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(TRUE, 2, "lofar2_unb2b_ring_full", c_nof_rn, 3, 1) PORT MAP(tb_end(2)); -- access scheme 1.
u_full_2_3 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(TRUE, 3, "lofar2_unb2b_ring_full", c_nof_rn, 32, 2) PORT MAP(tb_end(3)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
-- u_16_rn -> Using 16 ring nodes. Using the _one revision as it only uses 1 lane to limit MM readout time. Also using
-- g_nof_block_per_sync = 32 as all bsn monitors have to be read during one sync period which takes more time with 16 nodes.
u_16_rn : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(TRUE, 4, "lofar2_unb2b_ring_one", 16, 32, 2) PORT MAP(tb_end(4));
tb_end_and <= vector_and(tb_end);
proc_common_stop_simulation(tb_end_and);
END tb;
applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
+ 49
− 46
View file @ 8ba771b9
......@@ -52,18 +52,23 @@ USE work.lofar2_unb2c_ring_pkg.ALL;
ENTITY tb_lofar2_unb2c_ring IS
GENERIC (
g_multi_tb : BOOLEAN := FALSE;
g_unb_nr : NATURAL := 0;
g_design_name : STRING := "lofar2_unb2c_ring_full";
g_design_name : STRING := "lofar2_unb2c_ring_one";
g_nof_rn : NATURAL := 3;
g_nof_block_per_sync : NATURAL := 3;
g_access_scheme : INTEGER RANGE 1 TO 3 := 1
);
PORT (
tb_end : OUT STD_LOGIC := '0' -- For multi tb
);
END tb_lofar2_unb2c_ring;
ARCHITECTURE tb OF tb_lofar2_unb2c_ring IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_node_nr : NATURAL := 0;
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(g_unb_nr, c_unb2c_board_nof_uniboard_w) & TO_UVEC(0, c_unb2c_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0);
......@@ -82,11 +87,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ring IS
CONSTANT c_block_period : NATURAL := 1024;
CONSTANT c_blocksize : NATURAL := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size;
CONSTANT c_gapsize : NATURAL := c_block_period - c_blocksize;
CONSTANT c_nof_block_per_sync : NATURAL := 3;
CONSTANT c_sync_timeout : NATURAL := c_block_period * c_nof_block_per_sync + 10; -- +10 for extra slack
CONSTANT c_exp_bsn_at_sync : NATURAL := c_nof_block_per_sync;
CONSTANT c_exp_nof_sop : NATURAL := c_nof_block_per_sync;
CONSTANT c_exp_nof_valid : NATURAL := c_nof_block_per_sync * c_blocksize;
CONSTANT c_sync_timeout : NATURAL := c_block_period * g_nof_block_per_sync + 10; -- +10 for extra slack
CONSTANT c_exp_bsn_at_sync : NATURAL := g_nof_block_per_sync;
CONSTANT c_exp_nof_sop : NATURAL := g_nof_block_per_sync;
CONSTANT c_exp_nof_valid : NATURAL := g_nof_block_per_sync * c_blocksize;
-- MM
......@@ -100,7 +104,6 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ring IS
CONSTANT c_mm_file_reg_bsn_monitor_v2_ring_tx : STRING := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_RING_TX";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL tb_clk : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
......@@ -161,14 +164,14 @@ BEGIN
------------------------------------------------------------------------------
-- DUTs
------------------------------------------------------------------------------
gen_dut : FOR I IN 0 TO g_nof_rn -1 GENERATE
gen_dut_rn : FOR RN IN 0 TO g_nof_rn -1 GENERATE
u_lofar_unb2c_ring : ENTITY work.lofar2_unb2c_ring
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => "",
g_sim => c_sim,
g_sim_unb_nr => g_unb_nr,
g_sim_node_nr => I,
g_sim_unb_nr => g_unb_nr + (RN / c_quad),
g_sim_node_nr => RN MOD c_quad,
g_sim_sync_timeout => c_sync_timeout
)
PORT MAP (
......@@ -181,7 +184,7 @@ BEGIN
-- Others
VERSION => c_version,
ID => ( TO_UVEC(g_unb_nr, c_unb2c_board_nof_uniboard_w) & TO_UVEC(I, c_unb2c_board_nof_chip_w) ),
ID => ( TO_UVEC(RN / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC(RN MOD c_quad, c_unb2c_board_nof_chip_w) ),
TESTIO => open,
-- 1GbE Control Interface
......@@ -192,14 +195,14 @@ BEGIN
-- Transceiver clocks
SA_CLK => SA_CLK,
-- front transceivers
QSFP_0_RX => i_QSFP_0_RX(I),
QSFP_0_TX => i_QSFP_0_TX(I),
QSFP_0_RX => i_QSFP_0_RX(RN),
QSFP_0_TX => i_QSFP_0_TX(RN),
-- ring transceivers
RING_0_RX => i_RING_0_RX(I),
RING_0_TX => i_RING_0_TX(I),
RING_1_RX => i_RING_1_RX(I),
RING_1_TX => i_RING_1_TX(I),
RING_0_RX => i_RING_0_RX(RN),
RING_0_TX => i_RING_0_TX(RN),
RING_1_RX => i_RING_1_RX(RN),
RING_1_TX => i_RING_1_TX(RN),
-- LEDs
QSFP_LED => open
......@@ -232,8 +235,8 @@ BEGIN
-- Write ring configuration to all nodes.
FOR RN IN 0 TO g_nof_rn-1 LOOP
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_RING_INFO", 2, g_nof_rn, tb_clk); -- N_rn
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_RING_INFO", 3, 0, tb_clk); -- O_rn
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_INFO", 2, g_nof_rn, tb_clk); -- N_rn
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_INFO", 3, 0, tb_clk); -- O_rn
END LOOP;
-- Start node specific settings
......@@ -241,8 +244,8 @@ BEGIN
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk); -- use_ring_to_next_rn = 0
-- End node specific settings
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, g_nof_rn-1) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, g_nof_rn-1) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn-1) / c_quad), (g_nof_rn-1) MOD c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn-1) / c_quad), (g_nof_rn-1) MOD c_quad) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
----------------------------------------------------------------------------
-- Access scheme 1. A source RN creates the packets and sends them along the ring.
......@@ -264,11 +267,11 @@ BEGIN
FOR RN IN 0 TO g_nof_rn-1 LOOP
FOR I IN 0 TO c_nof_lanes-1 LOOP
-- Select both local and remote input on all nodes on all lanes.
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DP_XONOFF_LANE", I*2, 1, tb_clk); -- Enable input from lane
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DP_XONOFF_LOCAL", I*2, 1, tb_clk); -- Enable local input
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DP_XONOFF_LANE", I*2, 1, tb_clk); -- Enable input from lane
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DP_XONOFF_LOCAL", I*2, 1, tb_clk); -- Enable local input
-- Set transport_nof_hops to N_rn-1 on all nodes.
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_RING_LANE_INFO", I*2+1, g_nof_rn-1, tb_clk);
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_LANE_INFO", I*2+1, g_nof_rn-1, tb_clk);
END LOOP;
END LOOP;
END IF;
......@@ -276,10 +279,10 @@ BEGIN
-- Enable BG on all nodes (for bs_sosi)
----------------------------------------------------------------------------
FOR RN IN 0 TO g_nof_rn-1 LOOP
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 1, c_blocksize, tb_clk); -- samples per packet
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 2, c_nof_block_per_sync, tb_clk); -- blocks per sync
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 3, c_gapsize, tb_clk); -- gapsize
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 0, 3, tb_clk); -- enable at sync
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DIAG_BG", 1, c_blocksize, tb_clk); -- samples per packet
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DIAG_BG", 2, g_nof_block_per_sync, tb_clk); -- blocks per sync
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DIAG_BG", 3, c_gapsize, tb_clk); -- gapsize
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_DIAG_BG", 0, 3, tb_clk); -- enable at sync
END LOOP;
----------------------------------------------------------------------------
-- Verify Access scheme 1 by reading rx / tx monitors on source RN
......@@ -315,7 +318,7 @@ BEGIN
----------------------------------------------------------------------------
ELSE
-- Wait for bsn monitor to have received a sync period.
mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr, g_nof_rn-1) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn-1) / c_quad), (g_nof_rn-1) MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
"SIGNED", rd_data, ">", 0, -- this is the wait until condition
1 us, tb_clk); -- read every 1 us
......@@ -324,33 +327,33 @@ BEGIN
FOR J IN 0 TO g_nof_rn-1 LOOP -- bsn_monitor index
-- No packets transmitted from next RN (this_rn + 1 for even lanes, this_rn - 1 for odd lanes) as this RN should have removed it from the ring.
IF (I MOD 2 = 0 AND (RN + 1) MOD g_nof_rn = J) OR (I MOD 2 = 1 AND (RN + g_nof_rn-1) MOD g_nof_rn = J) THEN
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
ASSERT rd_data(2) = '1' REPORT "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
ELSE
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
ASSERT rd_data(2) = '0' REPORT "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
ASSERT TO_UINT(rd_data) = c_exp_nof_sop REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
ASSERT TO_UINT(rd_data) = c_exp_nof_valid REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+5, rd_data, tb_clk); --nof_err
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+5, rd_data, tb_clk); --nof_err
ASSERT TO_UINT(rd_data) = 0 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
END IF;
IF RN = J THEN -- No packets received from itself as the previous RN should have removed it from the ring.
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
ASSERT rd_data(2) = '1' REPORT "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
ELSE
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
ASSERT rd_data(2) = '0' REPORT "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
ASSERT TO_UINT(rd_data) = c_exp_nof_sop REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
ASSERT TO_UINT(rd_data) = c_exp_nof_valid REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+5, rd_data, tb_clk); --nof_err
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+5, rd_data, tb_clk); --nof_err
ASSERT TO_UINT(rd_data) = 0 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
END IF;
END LOOP;
......@@ -363,7 +366,7 @@ BEGIN
---------------------------------------------------------------------------
sim_done <= '1';
proc_common_wait_some_cycles(ext_clk, 100);
proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, tb_end);
WAIT;
END PROCESS;
......
applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
+ 25
− 11
View file @ 8ba771b9
......@@ -27,24 +27,38 @@
-- > run -all
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.common_pkg.ALL;
ENTITY tb_tb_lofar2_unb2c_ring IS
END tb_tb_lofar2_unb2c_ring;
ARCHITECTURE tb OF tb_tb_lofar2_unb2c_ring IS
CONSTANT c_nof_rn : NATURAL := 3;
SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
CONSTANT c_nof_tb : NATURAL := 5;
SIGNAL tb_end : STD_LOGIC_VECTOR(c_nof_tb-1 DOWNTO 0) := (OTHERS => '0'); -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
SIGNAL tb_end_and : STD_LOGIC;
BEGIN
-- g_unb_nr : NATURAL := 0;
-- g_design_name : STRING := "lofar2_unb2c_ring_full";
-- g_nof_rn : NATURAL := 3;
-- g_access_scheme : INTEGER RANGE 1 TO 3 := 1
-- g_multi_tb : BOOLEAN := FALSE;
-- g_unb_nr : NATURAL := 4;
-- g_design_name : STRING := "lofar2_unb2c_ring_one";
-- g_nof_rn : NATURAL := 16;
-- g_nof_block_per_sync : NATURAL := 32;
-- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
-- using different g_unb_nr to avoid MM file clashing.
u_one_1 : ENTITY work.tb_lofar2_unb2c_ring GENERIC MAP(0, "lofar2_unb2c_ring_one", c_nof_rn, 1); -- access scheme 1.
u_one_2_3 : ENTITY work.tb_lofar2_unb2c_ring GENERIC MAP(1, "lofar2_unb2c_ring_one", c_nof_rn, 2); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_full_1 : ENTITY work.tb_lofar2_unb2c_ring GENERIC MAP(2, "lofar2_unb2c_ring_full", c_nof_rn, 1); -- access scheme 1.
u_full_2_3 : ENTITY work.tb_lofar2_unb2c_ring GENERIC MAP(3, "lofar2_unb2c_ring_full", c_nof_rn, 2); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_one_1 : ENTITY work.tb_lofar2_unb2c_ring GENERIC MAP(TRUE, 0, "lofar2_unb2c_ring_one", c_nof_rn, 3, 1) PORT MAP(tb_end(0)); -- access scheme 1.
u_one_2_3 : ENTITY work.tb_lofar2_unb2c_ring GENERIC MAP(TRUE, 1, "lofar2_unb2c_ring_one", c_nof_rn, 3, 2) PORT MAP(tb_end(1)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_full_1 : ENTITY work.tb_lofar2_unb2c_ring GENERIC MAP(TRUE, 2, "lofar2_unb2c_ring_full", c_nof_rn, 3, 1) PORT MAP(tb_end(2)); -- access scheme 1.
u_full_2_3 : ENTITY work.tb_lofar2_unb2c_ring GENERIC MAP(TRUE, 3, "lofar2_unb2c_ring_full", c_nof_rn, 32, 2) PORT MAP(tb_end(3)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
-- u_16_rn -> Using 16 ring nodes. Using the _one revision as it only uses 1 lane to limit MM readout time. Also using
-- g_nof_block_per_sync = 32 as all bsn monitors have to be read during one sync period which takes more time with 16 nodes.
u_16_rn : ENTITY work.tb_lofar2_unb2c_ring GENERIC MAP(TRUE, 4, "lofar2_unb2c_ring_one", 16, 32, 2) PORT MAP(tb_end(4));
tb_end_and <= vector_and(tb_end);
proc_common_stop_simulation(tb_end_and);
END tb;
libraries/base/ring/src/vhdl/ring_tx.vhd
+ 1
− 1
View file @ 8ba771b9
......@@ -78,7 +78,7 @@ ARCHITECTURE str OF ring_tx IS
CONSTANT c_nof_hdr_fields : NATURAL := sel_a_b(g_use_dp_layer, c_ring_dp_nof_hdr_fields, c_ring_eth_nof_hdr_fields);
CONSTANT c_hdr_field_sel : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_sel, c_ring_eth_hdr_field_sel);
CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_arr, c_ring_eth_hdr_field_arr);
CONSTANT c_fifo_size : NATURAL := 8; -- Large enough to fit ETH/DP header (choose power of 2).
CONSTANT c_fifo_size : NATURAL := 64; -- Large enough to fit ETH/DP header + slack (choose power of 2).
SIGNAL validated_sosi : t_dp_sosi;
SIGNAL tx_sosi : t_dp_sosi;
......
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