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Commit 8b28ffeb authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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add internal fpga voltage sensor to unb2_minimal

parent 2bf0ea39
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boards/uniboard2/designs/unb2_minimal/quartus/qsys_unb2_minimal.qsys
+ 160
− 22
View file @ 8b28ffeb
...@@ -125,6 +125,11 @@ ...@@ -125,6 +125,11 @@
value = "12"; value = "12";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element pio_pps.mem element pio_pps.mem
{ {
...@@ -141,6 +146,11 @@ ...@@ -141,6 +146,11 @@
value = "11"; value = "11";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element pio_system_info.mem element pio_system_info.mem
{ {
...@@ -173,6 +183,11 @@ ...@@ -173,6 +183,11 @@
value = "16"; value = "16";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element reg_dpmm_ctrl.mem element reg_dpmm_ctrl.mem
{ {
...@@ -189,6 +204,11 @@ ...@@ -189,6 +204,11 @@
value = "17"; value = "17";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element reg_dpmm_data.mem element reg_dpmm_data.mem
{ {
...@@ -205,6 +225,11 @@ ...@@ -205,6 +225,11 @@
value = "15"; value = "15";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element reg_epcs.mem element reg_epcs.mem
{ {
...@@ -214,7 +239,7 @@ ...@@ -214,7 +239,7 @@
type = "String"; type = "String";
} }
} }
element reg_fpga_sens element reg_fpga_temp_sens
{ {
datum _sortIndex datum _sortIndex
{ {
...@@ -222,7 +247,7 @@ ...@@ -222,7 +247,7 @@
type = "int"; type = "int";
} }
} }
element reg_fpga_sens.mem element reg_fpga_temp_sens.mem
{ {
datum baseAddress datum baseAddress
{ {
...@@ -230,6 +255,27 @@ ...@@ -230,6 +255,27 @@
type = "String"; type = "String";
} }
} }
element reg_fpga_voltage_sens
{
datum _sortIndex
{
value = "20";
type = "int";
}
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
}
element reg_fpga_voltage_sens.mem
{
datum baseAddress
{
value = "512";
type = "String";
}
}
element reg_mmdp_ctrl element reg_mmdp_ctrl
{ {
datum _sortIndex datum _sortIndex
...@@ -237,6 +283,11 @@ ...@@ -237,6 +283,11 @@
value = "18"; value = "18";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element reg_mmdp_ctrl.mem element reg_mmdp_ctrl.mem
{ {
...@@ -253,6 +304,11 @@ ...@@ -253,6 +304,11 @@
value = "19"; value = "19";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element reg_mmdp_data.mem element reg_mmdp_data.mem
{ {
...@@ -269,6 +325,11 @@ ...@@ -269,6 +325,11 @@
value = "14"; value = "14";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element reg_remu.mem element reg_remu.mem
{ {
...@@ -317,6 +378,11 @@ ...@@ -317,6 +378,11 @@
value = "13"; value = "13";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element reg_wdi.mem element reg_wdi.mem
{ {
...@@ -338,6 +404,11 @@ ...@@ -338,6 +404,11 @@
value = "10"; value = "10";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element rom_system_info.mem element rom_system_info.mem
{ {
...@@ -654,38 +725,73 @@ ...@@ -654,38 +725,73 @@
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface <interface
name="reg_fpga_sens_address" name="reg_fpga_temp_sens_address"
internal="reg_fpga_sens.address" internal="reg_fpga_temp_sens.address"
type="conduit"
dir="end" />
<interface
name="reg_fpga_temp_sens_clk"
internal="reg_fpga_temp_sens.clk"
type="conduit"
dir="end" />
<interface
name="reg_fpga_temp_sens_read"
internal="reg_fpga_temp_sens.read"
type="conduit"
dir="end" />
<interface
name="reg_fpga_temp_sens_readdata"
internal="reg_fpga_temp_sens.readdata"
type="conduit"
dir="end" />
<interface
name="reg_fpga_temp_sens_reset"
internal="reg_fpga_temp_sens.reset"
type="conduit"
dir="end" />
<interface
name="reg_fpga_temp_sens_write"
internal="reg_fpga_temp_sens.write"
type="conduit"
dir="end" />
<interface
name="reg_fpga_temp_sens_writedata"
internal="reg_fpga_temp_sens.writedata"
type="conduit"
dir="end" />
<interface
name="reg_fpga_voltage_sens_address"
internal="reg_fpga_voltage_sens.address"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface <interface
name="reg_fpga_sens_clk" name="reg_fpga_voltage_sens_clk"
internal="reg_fpga_sens.clk" internal="reg_fpga_voltage_sens.clk"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface <interface
name="reg_fpga_sens_read" name="reg_fpga_voltage_sens_read"
internal="reg_fpga_sens.read" internal="reg_fpga_voltage_sens.read"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface <interface
name="reg_fpga_sens_readdata" name="reg_fpga_voltage_sens_readdata"
internal="reg_fpga_sens.readdata" internal="reg_fpga_voltage_sens.readdata"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface <interface
name="reg_fpga_sens_reset" name="reg_fpga_voltage_sens_reset"
internal="reg_fpga_sens.reset" internal="reg_fpga_voltage_sens.reset"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface <interface
name="reg_fpga_sens_write" name="reg_fpga_voltage_sens_write"
internal="reg_fpga_sens.write" internal="reg_fpga_voltage_sens.write"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface <interface
name="reg_fpga_sens_writedata" name="reg_fpga_voltage_sens_writedata"
internal="reg_fpga_sens.writedata" internal="reg_fpga_voltage_sens.writedata"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface <interface
...@@ -949,7 +1055,7 @@ ...@@ -949,7 +1055,7 @@
<parameter name="dataAddrWidth" value="18" /> <parameter name="dataAddrWidth" value="18" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" /> <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" /> <parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='reg_unb_pmbus.mem' start='0xC0' end='0xE0' /><slave name='reg_fpga_sens.mem' start='0xE0' end='0x100' /><slave name='timer_0.s1' start='0x100' end='0x120' /><slave name='reg_epcs.mem' start='0x120' end='0x140' /><slave name='reg_remu.mem' start='0x140' end='0x160' /><slave name='reg_unb_sens.mem' start='0x160' end='0x180' /><slave name='pio_wdi.s1' start='0x180' end='0x190' /><slave name='reg_mmdp_data.mem' start='0x190' end='0x198' /><slave name='reg_mmdp_ctrl.mem' start='0x198' end='0x1A0' /><slave name='reg_dpmm_data.mem' start='0x1A0' end='0x1A8' /><slave name='reg_dpmm_ctrl.mem' start='0x1A8' end='0x1B0' /><slave name='pio_pps.mem' start='0x1B0' end='0x1B8' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B8' end='0x1C0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter> <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='reg_unb_pmbus.mem' start='0xC0' end='0xE0' /><slave name='reg_fpga_temp_sens.mem' start='0xE0' end='0x100' /><slave name='timer_0.s1' start='0x100' end='0x120' /><slave name='reg_epcs.mem' start='0x120' end='0x140' /><slave name='reg_remu.mem' start='0x140' end='0x160' /><slave name='reg_unb_sens.mem' start='0x160' end='0x180' /><slave name='pio_wdi.s1' start='0x180' end='0x190' /><slave name='reg_mmdp_data.mem' start='0x190' end='0x198' /><slave name='reg_mmdp_ctrl.mem' start='0x198' end='0x1A0' /><slave name='reg_dpmm_data.mem' start='0x1A0' end='0x1A8' /><slave name='reg_dpmm_ctrl.mem' start='0x1A8' end='0x1B0' /><slave name='pio_pps.mem' start='0x1B0' end='0x1B8' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B8' end='0x1C0' /><slave name='reg_fpga_voltage_sens.mem' start='0x200' end='0x240' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" /> <parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" /> <parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" /> <parameter name="data_master_paddr_base" value="0" />
...@@ -1192,11 +1298,24 @@ ...@@ -1192,11 +1298,24 @@
<parameter name="g_adr_w" value="3" /> <parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" /> <parameter name="g_dat_w" value="32" />
</module> </module>
<module name="reg_fpga_sens" kind="avs_common_mm" version="1.0" enabled="1"> <module
name="reg_fpga_temp_sens"
kind="avs_common_mm"
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="3" /> <parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" /> <parameter name="g_dat_w" value="32" />
</module> </module>
<module
name="reg_fpga_voltage_sens"
kind="avs_common_mm"
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="4" />
<parameter name="g_dat_w" value="32" />
</module>
<module name="reg_mmdp_ctrl" kind="avs_common_mm" version="1.0" enabled="1"> <module name="reg_mmdp_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="1" /> <parameter name="g_adr_w" value="1" />
...@@ -1365,7 +1484,7 @@ ...@@ -1365,7 +1484,7 @@
kind="avalon" kind="avalon"
version="15.0" version="15.0"
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_fpga_sens.mem"> end="reg_fpga_temp_sens.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00e0" /> <parameter name="baseAddress" value="0x00e0" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
...@@ -1379,6 +1498,15 @@ ...@@ -1379,6 +1498,15 @@
<parameter name="baseAddress" value="0x00c0" /> <parameter name="baseAddress" value="0x00c0" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.0"
...@@ -1504,12 +1632,17 @@ ...@@ -1504,12 +1632,17 @@
kind="clock" kind="clock"
version="15.0" version="15.0"
start="clk_0.clk" start="clk_0.clk"
end="reg_fpga_sens.system" /> end="reg_fpga_temp_sens.system" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.0"
start="clk_0.clk" start="clk_0.clk"
end="reg_unb_pmbus.system" /> end="reg_unb_pmbus.system" />
<connection
kind="clock"
version="15.0"
start="clk_0.clk"
end="reg_fpga_voltage_sens.system" />
<connection <connection
kind="interrupt" kind="interrupt"
version="15.0" version="15.0"
...@@ -1612,7 +1745,7 @@ ...@@ -1612,7 +1745,7 @@
kind="reset" kind="reset"
version="15.0" version="15.0"
start="clk_0.clk_reset" start="clk_0.clk_reset"
end="reg_fpga_sens.system_reset" /> end="reg_fpga_temp_sens.system_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.0"
...@@ -1707,12 +1840,17 @@ ...@@ -1707,12 +1840,17 @@
kind="reset" kind="reset"
version="15.0" version="15.0"
start="cpu_0.debug_reset_request" start="cpu_0.debug_reset_request"
end="reg_fpga_sens.system_reset" /> end="reg_fpga_temp_sens.system_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.0"
start="cpu_0.debug_reset_request" start="cpu_0.debug_reset_request"
end="reg_unb_pmbus.system_reset" /> end="reg_unb_pmbus.system_reset" />
<connection
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_fpga_voltage_sens.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" /> <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
......
boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+ 20
− 10
View file @ 8b28ffeb
...@@ -57,8 +57,10 @@ ENTITY mmm_unb2_minimal IS ...@@ -57,8 +57,10 @@ ENTITY mmm_unb2_minimal IS
reg_unb_sens_mosi : OUT t_mem_mosi; reg_unb_sens_mosi : OUT t_mem_mosi;
reg_unb_sens_miso : IN t_mem_miso; reg_unb_sens_miso : IN t_mem_miso;
reg_fpga_sens_mosi : OUT t_mem_mosi; reg_fpga_temp_sens_mosi : OUT t_mem_mosi;
reg_fpga_sens_miso : IN t_mem_miso; reg_fpga_temp_sens_miso : IN t_mem_miso;
reg_fpga_voltage_sens_mosi: OUT t_mem_mosi;
reg_fpga_voltage_sens_miso: IN t_mem_miso;
reg_unb_pmbus_mosi : OUT t_mem_mosi; reg_unb_pmbus_mosi : OUT t_mem_mosi;
reg_unb_pmbus_miso : IN t_mem_miso; reg_unb_pmbus_miso : IN t_mem_miso;
...@@ -146,7 +148,7 @@ BEGIN ...@@ -146,7 +148,7 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso ); PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_SENS") u_mm_file_reg_fpga_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_SENS")
PORT MAP(mm_rst, mm_clk, reg_fpga_sens_mosi, reg_fpga_sens_miso ); PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS") u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso ); PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
...@@ -214,13 +216,21 @@ BEGIN ...@@ -214,13 +216,21 @@ BEGIN
reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd, reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w-1 DOWNTO 0), reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w-1 DOWNTO 0),
reg_fpga_sens_reset_export => OPEN, reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_sens_clk_export => OPEN, reg_fpga_temp_sens_clk_export => OPEN,
reg_fpga_sens_address_export => reg_fpga_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_sens_adr_w-1 DOWNTO 0), reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
reg_fpga_sens_write_export => reg_fpga_sens_mosi.wr, reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
reg_fpga_sens_writedata_export => reg_fpga_sens_mosi.wrdata(c_word_w-1 DOWNTO 0), reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_sens_read_export => reg_fpga_sens_mosi.rd, reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
reg_fpga_sens_readdata_export => reg_fpga_sens_miso.rddata(c_word_w-1 DOWNTO 0), reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_reset_export => OPEN,
reg_fpga_voltage_sens_clk_export => OPEN,
reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w-1 DOWNTO 0),
rom_system_info_reset_export => OPEN, rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN, rom_system_info_clk_export => OPEN,
......
boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
+ 14
− 7
View file @ 8b28ffeb
...@@ -129,13 +129,20 @@ PACKAGE qsys_unb2_minimal_pkg IS ...@@ -129,13 +129,20 @@ PACKAGE qsys_unb2_minimal_pkg IS
rom_system_info_reset_export : out std_logic; -- export rom_system_info_reset_export : out std_logic; -- export
rom_system_info_write_export : out std_logic; -- export rom_system_info_write_export : out std_logic; -- export
rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_fpga_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_fpga_sens_read_export : out std_logic; -- export reg_fpga_temp_sens_read_export : out std_logic; -- export
reg_fpga_sens_writedata_export : out std_logic_vector(31 downto 0); -- export reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
reg_fpga_sens_write_export : out std_logic; -- export reg_fpga_temp_sens_write_export : out std_logic; -- export
reg_fpga_sens_address_export : out std_logic_vector(2 downto 0); -- export reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
reg_fpga_sens_clk_export : out std_logic; -- export reg_fpga_temp_sens_clk_export : out std_logic; -- export
reg_fpga_sens_reset_export : out std_logic; -- export reg_fpga_temp_sens_reset_export : out std_logic; -- export
reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_fpga_voltage_sens_read_export : out std_logic; -- export
reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_fpga_voltage_sens_write_export : out std_logic; -- export
reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
reg_fpga_voltage_sens_clk_export : out std_logic; -- export
reg_fpga_voltage_sens_reset_export : out std_logic; -- export
reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_unb_pmbus_read_export : out std_logic; -- export reg_unb_pmbus_read_export : out std_logic; -- export
reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
......
boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+ 12
− 6
View file @ 8b28ffeb
...@@ -111,8 +111,10 @@ ARCHITECTURE str OF unb2_minimal IS ...@@ -111,8 +111,10 @@ ARCHITECTURE str OF unb2_minimal IS
SIGNAL reg_unb_sens_miso : t_mem_miso; SIGNAL reg_unb_sens_miso : t_mem_miso;
-- fpga sensors -- fpga sensors
SIGNAL reg_fpga_sens_mosi : t_mem_mosi; SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi;
SIGNAL reg_fpga_sens_miso : t_mem_miso; SIGNAL reg_fpga_temp_sens_miso : t_mem_miso;
SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi;
SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
-- pm bus -- pm bus
SIGNAL reg_unb_pmbus_mosi : t_mem_mosi; SIGNAL reg_unb_pmbus_mosi : t_mem_mosi;
...@@ -226,8 +228,10 @@ BEGIN ...@@ -226,8 +228,10 @@ BEGIN
reg_unb_sens_mosi => reg_unb_sens_mosi, reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso, reg_unb_sens_miso => reg_unb_sens_miso,
reg_fpga_sens_mosi => reg_fpga_sens_mosi, reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
reg_fpga_sens_miso => reg_fpga_sens_miso, reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
reg_unb_pmbus_mosi => reg_unb_pmbus_mosi, reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
reg_unb_pmbus_miso => reg_unb_pmbus_miso, reg_unb_pmbus_miso => reg_unb_pmbus_miso,
...@@ -301,8 +305,10 @@ BEGIN ...@@ -301,8 +305,10 @@ BEGIN
reg_unb_sens_mosi => reg_unb_sens_mosi, reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso, reg_unb_sens_miso => reg_unb_sens_miso,
reg_fpga_sens_mosi => reg_fpga_sens_mosi, reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
reg_fpga_sens_miso => reg_fpga_sens_miso, reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
reg_unb_pmbus_mosi => reg_unb_pmbus_mosi, reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
reg_unb_pmbus_miso => reg_unb_pmbus_miso, reg_unb_pmbus_miso => reg_unb_pmbus_miso,
......
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