Added dp_sync_checker

applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd

@@ -151,7 +151,10 @@ ENTITY mmm_apertif_unb1_fn_beamformer IS
                                     
     ram_ss_ss_wide_transp_mosi      : OUT t_mem_mosi;
     ram_ss_ss_wide_transp_miso      : IN  t_mem_miso := c_mem_miso_rst;
-                                    
+    
+    reg_dp_sync_checker_mosi        : OUT t_mem_mosi;
+    reg_dp_sync_checker_miso        : IN  t_mem_miso := c_mem_miso_rst;
+                                     
     -- IO DDR register map          
     reg_io_ddr_mosi                 : OUT t_mem_mosi;
     reg_io_ddr_miso                 : IN  t_mem_miso := c_mem_miso_rst;
@@ -166,7 +169,8 @@ ENTITY mmm_apertif_unb1_fn_beamformer IS
     -- . dp_xonoff
     reg_dp_xonoff_output_mosi       : OUT t_mem_mosi := c_mem_mosi_rst;
     reg_dp_xonoff_output_miso       : IN  t_mem_miso;                  
-
+    
+    -- . dp_switch
     reg_dp_switch_mosi              : OUT t_mem_mosi := c_mem_mosi_rst;
     reg_dp_switch_miso              : IN  t_mem_miso;             
 
@@ -199,8 +203,10 @@ ARCHITECTURE str OF mmm_apertif_unb1_fn_beamformer IS
   CONSTANT c_reg_bsn_monitor_output_adr_w        : NATURAL := 6; 
   CONSTANT c_reg_dp_xonoff_output_adr_w          : NATURAL := 1; 
   CONSTANT c_ram_diag_db_output_adr_w            : NATURAL := ceil_log2(g_bf.nof_bf_units*g_bf.nof_weights);
+  CONSTANT c_reg_diag_db_output_adr_w            : NATURAL := 5; --ceil_log2(g_bf.nof_bf_units)*3;
 
   CONSTANT c_ram_ss_ss_wide_transp_addr_w        : NATURAL := ceil_log2(g_reorder_seq.rd_chunksize*g_bf.nof_weights*2);     
+  CONSTANT c_reg_dp_sync_checker_addr_w          : NATURAL := 2;     
   CONSTANT c_mm_reg_io_ddr_addr_w                : NATURAL := ceil_log2(16);
   
   CONSTANT c_dp_reg_mm_nof_words                 : NATURAL := 1;
@@ -356,6 +362,9 @@ BEGIN
                                          
     u_mm_file_ram_ss_ss_wide_transp      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE_TRANSP")
                                                       PORT MAP(mm_rst, i_mm_clk, ram_ss_ss_wide_transp_mosi, ram_ss_ss_wide_transp_miso );
+
+    u_mm_file_reg_dp_sync_checker        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SYNC_CHECKER")
+                                                      PORT MAP(mm_rst, i_mm_clk, reg_dp_sync_checker_mosi, reg_dp_sync_checker_miso);
                                          
     u_mm_file_reg_io_ddr                 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
                                                       PORT MAP(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);                                
@@ -506,7 +515,7 @@ BEGIN
       coe_writedata_export_from_the_ram_diag_data_buffer_output => ram_diag_data_buf_output_mosi.wrdata(c_word_w-1 DOWNTO 0),
     
       -- the_reg_diag_data_buffer output
-      coe_address_export_from_the_reg_diag_data_buffer_output   => reg_diag_data_buf_output_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+      coe_address_export_from_the_reg_diag_data_buffer_output   => reg_diag_data_buf_output_mosi.address(c_reg_diag_db_output_adr_w-1 DOWNTO 0),
       coe_clk_export_from_the_reg_diag_data_buffer_output       => OPEN,
       coe_read_export_from_the_reg_diag_data_buffer_output      => reg_diag_data_buf_output_mosi.rd,
       coe_readdata_export_to_the_reg_diag_data_buffer_output    => reg_diag_data_buf_output_miso.rddata(c_word_w-1 DOWNTO 0),
@@ -628,6 +637,15 @@ BEGIN
       coe_reset_export_from_the_ram_ss_ss_wide_transp         => OPEN,                                            
       coe_write_export_from_the_ram_ss_ss_wide_transp         => ram_ss_ss_wide_transp_mosi.wr,                                  
       coe_writedata_export_from_the_ram_ss_ss_wide_transp     => ram_ss_ss_wide_transp_mosi.wrdata(c_word_w-1 DOWNTO 0),         
+
+      -- the_ram_ss_ss_transpose
+      coe_address_export_from_the_reg_dp_sync_checker         => reg_dp_sync_checker_mosi.address(c_reg_dp_sync_checker_addr_w-1 DOWNTO 0), 
+      coe_clk_export_from_the_reg_dp_sync_checker             => OPEN,                                            
+      coe_read_export_from_the_reg_dp_sync_checker            => reg_dp_sync_checker_mosi.rd,                                  
+      coe_readdata_export_to_the_reg_dp_sync_checker          => reg_dp_sync_checker_miso.rddata(c_word_w-1 DOWNTO 0),         
+      coe_reset_export_from_the_reg_dp_sync_checker           => OPEN,                                            
+      coe_write_export_from_the_reg_dp_sync_checker           => reg_dp_sync_checker_mosi.wr,                                  
+      coe_writedata_export_from_the_reg_dp_sync_checker       => reg_dp_sync_checker_mosi.wrdata(c_word_w-1 DOWNTO 0),         
       
       -- the_reg_io_ddr
       coe_address_export_from_the_reg_io_ddr                   => reg_io_ddr_mosi.address(c_mm_reg_io_ddr_addr_w-1 DOWNTO 0),