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RTSD
HDL
Commits
88010aa0
Commit
88010aa0
authored
10 years ago
by
Daniel van der Schuur
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-Removed override interface.
parent
94b2786c
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libraries/base/dp/src/vhdl/dp_field_blk.vhd
+22
-22
22 additions, 22 deletions
libraries/base/dp/src/vhdl/dp_field_blk.vhd
with
22 additions
and
22 deletions
libraries/base/dp/src/vhdl/dp_field_blk.vhd
+
22
−
22
View file @
88010aa0
...
...
@@ -107,16 +107,16 @@ ENTITY dp_field_blk IS
-- slv_out_val : OUT STD_LOGIC;
reg_slv_mosi
:
IN
t_mem_mosi
:
=
c_mem_mosi_rst
;
reg_slv_miso
:
OUT
t_mem_miso
;
reg_slv_miso
:
OUT
t_mem_miso
reg_ovr_mosi
:
IN
t_mem_mosi
:
=
c_mem_mosi_rst
;
reg_ovr_miso
:
OUT
t_mem_miso
--
reg_ovr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
--
reg_ovr_miso : OUT t_mem_miso
);
END
dp_field_blk
;
ARCHITECTURE
str
OF
dp_field_blk
IS
CONSTANT
c_ovr_field_arr
:
t_common_field_arr
(
g_field_arr
'RANGE
)
:
=
field_ovr_arr
(
g_field_arr
,
g_field_sel
);
--
CONSTANT c_ovr_field_arr : t_common_field_arr(g_field_arr'RANGE) := field_ovr_arr(g_field_arr, g_field_sel);
-- Mode: fields to data block (c_field_to_block=True) or data block to fields (c_field_to_block=False)
-- a.k.a. wire to narrow or narrow to wide
...
...
@@ -130,7 +130,7 @@ ARCHITECTURE str OF dp_field_blk IS
SIGNAL
mm_fields_slv_in_val
:
STD_LOGIC
;
SIGNAL
mm_fields_slv_out
:
STD_LOGIC_VECTOR
(
c_mm_fields_slv_out_w
-1
DOWNTO
0
);
SIGNAL
field_override_arr
:
STD_LOGIC_VECTOR
(
g_field_arr
'RANGE
);
--1 override bit per field
SIGNAL
field_override_arr
:
STD_LOGIC_VECTOR
(
g_field_arr
'RANGE
)
:
=
g_field_sel
;
--1 override bit per field
SIGNAL
dp_repack_data_snk_in
:
t_dp_sosi
;
SIGNAL
dp_repack_data_snk_out
:
t_dp_siso
;
...
...
@@ -221,22 +221,22 @@ BEGIN
---------------------------------------------------------------------------------------
-- mm_fields to set override bits
---------------------------------------------------------------------------------------
u_mm_fields_ovr
:
ENTITY
mm_lib
.
mm_fields
GENERIC
MAP
(
g_field_arr
=>
field_arr_set_mode
(
c_ovr_field_arr
,
"RW"
)
-- override fields are always RW
)
PORT
MAP
(
mm_clk
=>
mm_clk
,
mm_rst
=>
mm_rst
,
mm_mosi
=>
reg_ovr_mosi
,
mm_miso
=>
reg_ovr_miso
,
slv_clk
=>
dp_clk
,
slv_rst
=>
dp_rst
,
slv_out
=>
field_override_arr
);
--
---------------------------------------------------------------------------------------
--
u_mm_fields_ovr: ENTITY mm_lib.mm_fields
--
GENERIC MAP(
--
g_field_arr => field_arr_set_mode(c_ovr_field_arr, "RW") -- override fields are always RW
--
)
--
PORT MAP (
--
mm_clk => mm_clk,
--
mm_rst => mm_rst,
--
--
mm_mosi => reg_ovr_mosi,
--
mm_miso => reg_ovr_miso,
--
--
slv_clk => dp_clk,
--
slv_rst => dp_rst,
--
--
slv_out => field_override_arr
--
);
END
str
;
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