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Commit 87fdde83 authored by Eric Kooistra's avatar Eric Kooistra
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Merge branch 'master' of git.astron.nl:rtsd/hdl

parents 01949ac4 cf3c0b73
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libraries/technology/ip_agi027_xxxx/mult_add2/ip_agi027_xxxx_mult_add2_rtl.vhd → libraries/technology/ip_agi027_1e1v/mult_add2/ip_agi027_1e1v_mult_add2_rtl.vhd
+ 3
− 3
View file @ 87fdde83
......@@ -36,7 +36,7 @@ use common_lib.common_pkg.all;
-- . res = a0 * b0 - a1 * b1
------------------------------------------------------------------------------
entity ip_agi027_xxxx_mult_add2_rtl is
entity ip_agi027_1e1v_mult_add2_rtl is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
......@@ -57,9 +57,9 @@ entity ip_agi027_xxxx_mult_add2_rtl is
in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
res : out std_logic_vector(g_res_w - 1 downto 0)
);
end ip_agi027_xxxx_mult_add2_rtl;
end ip_agi027_1e1v_mult_add2_rtl;
architecture str of ip_agi027_xxxx_mult_add2_rtl is
architecture str of ip_agi027_1e1v_mult_add2_rtl is
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
......
libraries/technology/ip_agi027_xxxx/mult_add4/compile_ip.tcl → libraries/technology/ip_agi027_1e1v/mult_add4/compile_ip.tcl
+ 4
− 4
View file @ 87fdde83
......@@ -28,11 +28,11 @@
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_mult_add4/sim"
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_mult_add4/sim"
vmap ip_agi027_xxxx_mult_add4 ./work/
vmap ip_agi027_1e1v_mult_add4 ./work/
vmap altera_mult_add_1920 ./work/
vcom "$IP_DIR/../altera_mult_add_1920/sim/ip_agi027_xxxx_mult_add4_altera_mult_add_1920_ljq3huq.vhd" -work altera_mult_add_1920
vcom "$IP_DIR/ip_agi027_xxxx_mult_add4.vhd" -work ip_agi027_xxxx_mult_add4
vcom "$IP_DIR/../altera_mult_add_1920/sim/ip_agi027_1e1v_mult_add4_altera_mult_add_1920_ljq3huq.vhd" -work altera_mult_add_1920
vcom "$IP_DIR/ip_agi027_1e1v_mult_add4.vhd" -work ip_agi027_1e1v_mult_add4
libraries/technology/ip_agi027_xxxx/mult_add4/hdllib.cfg → libraries/technology/ip_agi027_1e1v/mult_add4/hdllib.cfg
+ 21
− 0
View file @ 87fdde83
hdl_lib_name = ip_agi027_xxxx_mult_add4
hdl_library_clause_name = ip_agi027_xxxx_mult_add4_lib
hdl_lib_name = ip_agi027_1e1v_mult_add4
hdl_library_clause_name = ip_agi027_1e1v_mult_add4_lib
hdl_lib_uses_synth = technology common
hdl_lib_uses_sim =
hdl_lib_technology = ip_agi027_xxxx
hdl_lib_technology = ip_agi027_1e1v
synth_files =
ip_agi027_xxxx_mult_add4_rtl.vhd
ip_agi027_1e1v_mult_add4_rtl.vhd
test_bench_files =
......@@ -17,5 +17,5 @@ test_bench_files =
[generate_ip_libs]
qsys-generate_ip_files =
ip_agi027_xxxx_mult_add4.ip
ip_agi027_1e1v_mult_add4.ip
libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4.ip → libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4.ip
+ 2
− 2
View file @ 87fdde83
......@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_agi027_xxxx_mult_add4</ipxact:library>
<ipxact:library>ip_agi027_1e1v_mult_add4</ipxact:library>
<ipxact:name>mult_add_0</ipxact:name>
<ipxact:version>19.2.0</ipxact:version>
<ipxact:busInterfaces>
......@@ -799,7 +799,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_agi027_xxxx_mult_add4</ipxact:library>
<ipxact:library>ip_agi027_1e1v_mult_add4</ipxact:library>
<ipxact:name>altera_mult_add</ipxact:name>
<ipxact:version>19.2.0</ipxact:version>
</altera:entity_info>
......
libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4_rtl.vhd → libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4_rtl.vhd
+ 3
− 3
View file @ 87fdde83
......@@ -32,7 +32,7 @@ use common_lib.common_pkg.all;
-- Function:
-- . res = (a0 * b0 +- a1 * b1) +- (a2 * b2 +- a3 * b3)
entity ip_agi027_xxxx_mult_add4_rtl is
entity ip_agi027_1e1v_mult_add4_rtl is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
......@@ -55,9 +55,9 @@ entity ip_agi027_xxxx_mult_add4_rtl is
in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
res : out std_logic_vector(g_res_w - 1 downto 0)
);
end ip_agi027_xxxx_mult_add4_rtl;
end ip_agi027_1e1v_mult_add4_rtl;
architecture str of ip_agi027_xxxx_mult_add4_rtl is
architecture str of ip_agi027_1e1v_mult_add4_rtl is
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
......
libraries/technology/ip_agi027_xxxx/ram/README.txt → libraries/technology/ip_agi027_1e1v/ram/README.txt
+ 30
− 30
View file @ 87fdde83
README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/ram
README.txt for $HDL_WORK/libraries/technology/ip_agi027_1e1v/ram
VERSION 02 - 20231218
Contents:
......@@ -19,23 +19,23 @@ Contents:
1) RAM components:
Available:
ip_agi027_xxxx_ram_cr_cw = One read port with clock and one write port with clock and with separate address and same data width on both ports.
ip_agi027_xxxx_ram_crk_cw = One read port with clock and one write port with clock and with separate address and different data withs on both ports.
ip_agi027_1e1v_ram_cr_cw = One read port with clock and one write port with clock and with separate address and same data width on both ports.
ip_agi027_1e1v_ram_crk_cw = One read port with clock and one write port with clock and with separate address and different data withs on both ports.
The data port widths maintain a power of two ratio between them.
ip_agi027_xxxx_ram_r_w = Single clock, one read port and one write port and with separate address and same data width on both ports.
ip_agi027_xxxx_ram_rw_rw = Two read/write ports each port with same clock and with separate address per port and same data width on both ports.
ip_agi027_1e1v_ram_r_w = Single clock, one read port and one write port and with separate address and same data width on both ports.
ip_agi027_1e1v_ram_rw_rw = Two read/write ports each port with same clock and with separate address per port and same data width on both ports.
Unavailable:
ip_agi027_xxxx_ram_crw_crw = Two read/write ports each port with own port clock and with separate address and same data width on both ports.
ip_agi027_1e1v_ram_crw_crw = Two read/write ports each port with own port clock and with separate address and same data width on both ports.
For the Agilex 7 this IP can only be generated with 'Emulate TDP dual clock mode' and what this entails is described
under '8) Agilex7 issues'. With this mandatory enable option, this IP is not supported as used for previous technologies.
ip_agi027_xxxx_ram_crwk_crw = Two read/write ports each port with own port clock and with power of two ratio between port widths.
ip_agi027_1e1v_ram_crwk_crw = Two read/write ports each port with own port clock and with power of two ratio between port widths.
Not available, because the Agilex 7 does not support ratio widths in combination with true dual port mode.
2) ROM components:
ip_agi027_xxxx_rom_r_w = Not available and not needed, because the ip_agi027_xxxx_ram_r_w can be used for ROM IP by not connecting the
ip_agi027_1e1v_rom_r_w = Not available and not needed, because the ip_agi027_1e1v_ram_r_w can be used for ROM IP by not connecting the
write port. The IP could be created and than the vhd file can be derived from the generated HDL files and the
existing ip_stratixiv_rom_r.vhd file.
......@@ -43,49 +43,49 @@ Contents:
3) Agilex7 IP
The RAM IPs were ported manually from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_xxxx by creating it in Quartus
The RAM IPs were ported manually from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_1e1v by creating it in Quartus
using the same parameter settings by:
- method A:
. copy original ip_arria_e2sg_<ram_name>.vhd and ip_arria_e2sg_<ram_name>.ip files.
. rename ip_arria_e2sg_<ram_name>.ip and .vhd into ip_agi027_xxxx_<ram_name>.ip and .vhd (also replace name inside the .vhd file)
. rename ip_arria_e2sg_<ram_name>.ip and .vhd into ip_agi027_1e1v_<ram_name>.ip and .vhd (also replace name inside the .vhd file)
. open in to Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
Finish automatically convert to "new" IP, note differences such as version.
. then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build directory using the
terminal command generate_ip_libs <buildset> and finish to save the changes.
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
necessary to make it work.
. git commit also the ip_agi027_xxxx_<ram_name>.ip to preserve the original in case it needs to be modified.
. git commit also the ip_agi027_1e1v_<ram_name>.ip to preserve the original in case it needs to be modified.
- method B:
. copy original ip_arria_e2sg_<ram_name>.vhd file.
. rename ip_arria_e2sg_<ram_name>.vhd into ip_agi027_xxxx_<ram_name>.vhd (also replace name inside the .vhd file).
. rename ip_arria_e2sg_<ram_name>.vhd into ip_agi027_1e1v_<ram_name>.vhd (also replace name inside the .vhd file).
. open ip_arria_e2sg_<ram_name>.ip file in Quartus 19.4.0 build 64. No device family and device part need to be set.
. open also Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
. select the corresponding IP in the IP catalog in Quartus 23.2.0 and provide the filename as ip_agi027_xxxx_<ram_name>.ip
. select the corresponding IP in the IP catalog in Quartus 23.2.0 and provide the filename as ip_agi027_1e1v_<ram_name>.ip
Finish automatically convert to IP, note differences such as version.
. save the changes and then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build
directory using the terminal command generate_ip_libs <buildset> to finish it.
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
necessary to make it work.
. git commit also the ip_agi027_xxxx_<ram_name>.ip to preserve the original if case it needs to be modified.
. git commit also the ip_agi027_1e1v_<ram_name>.ip to preserve the original if case it needs to be modified.
this yields:
ip_agi027_xxxx_ram_cr_cw.ip
ip_agi027_xxxx_ram_crk_cw.ip
ip_agi027_1e1v_ram_cr_cw.ip
ip_agi027_1e1v_ram_crk_cw.ip
is derived from the ip_arria10_e2sg_ram_crwk_crw by modifying it to feature a single read and a single write port,
and incorporating a dual-clock design with distinct clocks for reading and writing.
ip_agi027_xxxx_ram_r_w.ip
ip_agi027_xxxx_ram_rw_rw.ip
ip_agi027_1e1v_ram_r_w.ip
ip_agi027_1e1v_ram_rw_rw.ip
is derived from the ip_arria10_e2sg_ram_crw_crw, incorporating the modification to operate with a single clock.
The IP only needs to be generated with generate_ip_libs <buildset> if it need to be modified, because the ip_agi027_xxxx_ram_*.vhd
directly instantiates the altera_syncram component. The buildset for the agi027_xxxx is iwave.
The IP only needs to be generated with generate_ip_libs <buildset> if it need to be modified, because the ip_agi027_1e1v_ram_*.vhd
directly instantiates the altera_syncram component. The buildset for the agi027_1e1v is iwave.
The instantiation is copied manually from the ip_agi027_xxxx_ram_*/ram_2port_2040/sim/ip_agi027_xxxx_ram_*.vhd and saved in the
ip_agi027_xxxx_<ram_name>.vhd file. So the generated HDL files are no longer needed, because it could easily be derived
The instantiation is copied manually from the ip_agi027_1e1v_ram_*/ram_2port_2040/sim/ip_agi027_1e1v_ram_*.vhd and saved in the
ip_agi027_1e1v_<ram_name>.vhd file. So the generated HDL files are no longer needed, because it could easily be derived
from the IP file and the files will be generated in the build directory (under iwave/qsys-generate/) when using the terminal command
generate_ip_libs <buildset>.
......@@ -149,9 +149,9 @@ Contents:
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_xxxx/ram/quartus/ram.qsf could be added to the hdllib.cfg under
quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_1e1v/ram/quartus/ram.qsf could be added to the hdllib.cfg under
[quartus_project_file]. Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
The Quartus project ip_agi027_xxxx_ram.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_xxxx_ram/ was used to verify that the block RAM IP
The Quartus project ip_agi027_1e1v_ram.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_1e1v_ram/ was used to verify that the block RAM IP
actually synthesise to the appropriate FPGA resources. The current version of the inferred RAM is verified at arria10. Use the Quartus
GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file in the file tab of the Quartus
project navigator window. For the (default) testcondition the generics are set to 32 words memory size and 8 bits wide. They only differ
......@@ -188,7 +188,7 @@ Contents:
8) Agilex7 issues
No (direct) available use of ip_agi027_xxxx_ram_crw_crw and *_crwk_crw. The other .vhd synth files based on generated HDL files of the IPs did not
No (direct) available use of ip_agi027_1e1v_ram_crw_crw and *_crwk_crw. The other .vhd synth files based on generated HDL files of the IPs did not
encounter any issues.
crw_crw (dual-clock-read-write port RAM):
......@@ -212,7 +212,7 @@ Contents:
. the FIFO depth must be a power of 2 and must exceed the clock frequency ratio (B/A) to ensure the proper functioning of the emulated TDP.
-Solution:
This results in the utilization of a newly created IP, ip_agi027_xxxx_ram_rw_rw, which is a single-clock dual-read-write RAM, instead of *_crw_crw. And
This results in the utilization of a newly created IP, ip_agi027_1e1v_ram_rw_rw, which is a single-clock dual-read-write RAM, instead of *_crw_crw. And
address the solution at the higher-level layers where the implementation is occurring. This is appropriate due to the structure of the HDL git repository.
For this new IP, tech_memory_ram_rw_rw is created, wherein rw_rw functionality is constructed for the previous technology identifiers using the crw_crw
IP synthesis files in only one clock domain by providing the same clock signal twice, and no new rw_rw IPs need to be generated.
......@@ -222,13 +222,13 @@ Contents:
crwk_crw (dual-clock-read-write port with a power of two data width ratio):
-Cause:
Due to the errors that occurs in the Quartus configuration (refer to [5], [6] and [7]), the ip_agi027_xxxx_ram_crwk_crw cannot be ported.
Due to the errors that occurs in the Quartus configuration (refer to [5], [6] and [7]), the ip_agi027_1e1v_ram_crwk_crw cannot be ported.
This IP has also the same issue due to the clocking method as crw_crw, but also has additonal issues due to incompatibility for different data withs
for true dual port RAM.
-Solution:
To facilitate a specific aspect of the functionality provided by crwk_crw, specifically its integration into common_ram_cr_cw_ratio, a newly IP,
ip_agi027_xxxx_crk_cw is created instead of *_crwk_crw. Which is a dual-clock simple-dual-read-write RAM. Unfortunately, there is no built-in
ip_agi027_1e1v_crk_cw is created instead of *_crwk_crw. Which is a dual-clock simple-dual-read-write RAM. Unfortunately, there is no built-in
implementation or solution for achieving the same functionality as crwk_crw for backward compatibility with Arria10 in the Quartus tool.
This implies that a custom implementation must be created at higher-level layers to achieve this functionality.
For this new IP, tech_memory_ram_crk_cw is created, wherein crk_cw functionality is made compatible for the existing technology identifiers using the crwk_crw
......@@ -240,11 +240,11 @@ Contents:
9) Remarks:
a) For tech_memory_ram_crw_crw the ip_agi027_xxxx_rw_rw is added, because in a lot of files at the higher layer common_ram_crw_crw.vhd is used.
a) For tech_memory_ram_crw_crw the ip_agi027_1e1v_rw_rw is added, because in a lot of files at the higher layer common_ram_crw_crw.vhd is used.
It is not preferable to add an extra generic or the technology there, to generate the right used component.
So it is better to implement a clock domain cross component such as dp_fifo_dc_arr or common_reg_cross_domain (to save logic and/or RAM)
when needed at a design at the higher layer. A lot of designs cannot have an extra latency, and then one clock domain is also an option.
b) For tech_memory_ram_crwk_crw the ip_agi027_xxxx_rw_rw is added, because the ip_agi027_xxxx_crk_cw has one read and one write port and
b) For tech_memory_ram_crwk_crw the ip_agi027_1e1v_rw_rw is added, because the ip_agi027_1e1v_crk_cw has one read and one write port and
the mm port should have read/write possibility to check if standard rewrite to '0'-values is going well by writing other values then '0'
before to mm domain. To keep this therefore a DC_FIFO in combination with a MUX need to be added. (Also it is possible to check this with mm reg.)
And because only one clock domain is used in the other designs by the Agilex 7, ram_rw_rw makes the most suitable solution.
......
libraries/technology/ip_agi027_1e1v/ram/hdllib.cfg 0 → 100644
+ 24
− 0
View file @ 87fdde83
hdl_lib_name = ip_agi027_1e1v_ram
hdl_library_clause_name = ip_agi027_1e1v_ram_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
hdl_lib_technology = ip_agi027_1e1v
synth_files =
ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
ip_agi027_1e1v_simple_dual_port_ram_dual_clock.vhd
ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
ip_agi027_1e1v_ram_cr_cw.vhd
ip_agi027_1e1v_ram_crk_cw.vhd
ip_agi027_1e1v_ram_rw_rw.vhd
ip_agi027_1e1v_ram_r_w.vhd
test_bench_files =
[modelsim_project_file]
[quartus_project_file]
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.ip → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.ip
+ 2
− 2
View file @ 87fdde83
......@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_agi027_xxxx_ram_cr_cw</ipxact:library>
<ipxact:library>ip_agi027_1e1v_ram_cr_cw</ipxact:library>
<ipxact:name>ram_2port_0</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
<ipxact:busInterfaces>
......@@ -479,7 +479,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_agi027_xxxx_ram_cr_cw</ipxact:library>
<ipxact:library>ip_agi027_1e1v_ram_cr_cw</ipxact:library>
<ipxact:name>ram_2port</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
</altera:entity_info>
......
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.vhd → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd
+ 6
− 6
View file @ 87fdde83
......@@ -22,7 +22,7 @@
-- Purpose:
-- RadioHDL wrapper / Instantiate RAM IP with generics
-- Description:
-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_cr_cw_ram_2port_2040_cmcw2dy.vhd
-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_cr_cw_ram_2port_2040_cmcw2dy.vhd
library ieee, technology_lib;
use ieee.std_logic_1164.all;
......@@ -32,7 +32,7 @@ use technology_lib.technology_pkg.all;
library altera_lnsim;
use altera_lnsim.altera_lnsim_components.all;
entity ip_agi027_xxxx_ram_cr_cw is
entity ip_agi027_1e1v_ram_cr_cw is
generic (
g_inferred : boolean := false;
g_adr_w : natural := 5;
......@@ -50,9 +50,9 @@ entity ip_agi027_xxxx_ram_cr_cw is
wren : in std_logic := '0';
q : out std_logic_vector(g_dat_w - 1 downto 0)
);
end ip_agi027_xxxx_ram_cr_cw;
end ip_agi027_1e1v_ram_cr_cw;
architecture SYN of ip_agi027_xxxx_ram_cr_cw is
architecture SYN of ip_agi027_1e1v_ram_cr_cw is
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
......@@ -97,7 +97,7 @@ architecture SYN of ip_agi027_xxxx_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
u_altera_syncram : altera_syncram
......@@ -140,7 +140,7 @@ begin
rdaddr <= to_integer(unsigned(rdaddress));
wraddr <= to_integer(unsigned(wraddress));
u_mem : entity work.ip_agi027_xxxx_simple_dual_port_ram_dual_clock
u_mem : entity work.ip_agi027_1e1v_simple_dual_port_ram_dual_clock
generic map (
DATA_WIDTH => g_dat_w,
ADDR_WIDTH => g_adr_w
......
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.ip → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.ip
+ 2
− 2
View file @ 87fdde83
......@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_agi027_xxxx_ram_crk_cw</ipxact:library>
<ipxact:library>ip_agi027_1e1v_ram_crk_cw</ipxact:library>
<ipxact:name>ram_2port_0</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
<ipxact:busInterfaces>
......@@ -479,7 +479,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_agi027_xxxx_ram_crk_cw</ipxact:library>
<ipxact:library>ip_agi027_1e1v_ram_crk_cw</ipxact:library>
<ipxact:name>ram_2port</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
</altera:entity_info>
......
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.vhd → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd
+ 6
− 6
View file @ 87fdde83
......@@ -27,9 +27,9 @@
-- Port b is only used for read in read clock domain
-- Reference:
-- Copied component declaration and instance example from
-- generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_crk_cw_ram_2port_2040_aadk55y.vhd
-- generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_crk_cw_ram_2port_2040_aadk55y.vhd
-- Remark:
-- Created this IP for the Agilex 7 (agi027_xxxx) due to incompatibility with
-- Created this IP for the Agilex 7 (agi027_1e1v) due to incompatibility with
-- the standard crwk_crw IP variant, to facilitate its integration into
-- common_ram_cr_cw_ratio.
......@@ -41,7 +41,7 @@ use technology_lib.technology_pkg.all;
library altera_lnsim;
use altera_lnsim.altera_lnsim_components.all;
entity ip_agi027_xxxx_ram_crk_cw is
entity ip_agi027_1e1v_ram_crk_cw is
generic (
g_wr_adr_w : natural := 5;
g_wr_dat_w : natural := 32;
......@@ -61,9 +61,9 @@ entity ip_agi027_xxxx_ram_crk_cw is
rdclk : in std_logic;
q : out std_logic_vector(g_rd_dat_w - 1 downto 0)
);
end ip_agi027_xxxx_ram_crk_cw;
end ip_agi027_1e1v_ram_crk_cw;
architecture SYN of ip_agi027_xxxx_ram_crk_cw is
architecture SYN of ip_agi027_1e1v_ram_crk_cw is
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
......@@ -103,7 +103,7 @@ architecture SYN of ip_agi027_xxxx_ram_crk_cw is
end component;
begin
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_crk_cw : read latency must be 1 (default) or 2" severity FAILURE;
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_crk_cw : read latency must be 1 (default) or 2" severity FAILURE;
u_altera_syncram : altera_syncram
generic map (
......
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.ip → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.ip
+ 2
− 2
View file @ 87fdde83
......@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_agi027_xxxx_ram_r_w</ipxact:library>
<ipxact:library>ip_agi027_1e1v_ram_r_w</ipxact:library>
<ipxact:name>ram_2port_0</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
<ipxact:busInterfaces>
......@@ -420,7 +420,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_agi027_xxxx_ram_r_w</ipxact:library>
<ipxact:library>ip_agi027_1e1v_ram_r_w</ipxact:library>
<ipxact:name>ram_2port</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
</altera:entity_info>
......
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.vhd → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd
+ 6
− 6
View file @ 87fdde83
......@@ -22,7 +22,7 @@
-- Purpose:
-- RadioHDL wrapper / Instantiate RAM IP with generics
-- Description:
-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_r_w_ram_2port_2040_gbkw2ny.vhd
-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_r_w_ram_2port_2040_gbkw2ny.vhd
library ieee, technology_lib;
use ieee.std_logic_1164.all;
......@@ -32,7 +32,7 @@ use technology_lib.technology_pkg.all;
library altera_lnsim;
use altera_lnsim.altera_lnsim_components.all;
entity ip_agi027_xxxx_ram_r_w is
entity ip_agi027_1e1v_ram_r_w is
generic (
g_inferred : boolean := false;
g_adr_w : natural := 5;
......@@ -49,9 +49,9 @@ entity ip_agi027_xxxx_ram_r_w is
wren : in std_logic := '0';
q : out std_logic_vector(g_dat_w - 1 downto 0)
);
end ip_agi027_xxxx_ram_r_w;
end ip_agi027_1e1v_ram_r_w;
architecture SYN of ip_agi027_xxxx_ram_r_w is
architecture SYN of ip_agi027_1e1v_ram_r_w is
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
component altera_syncram
......@@ -95,7 +95,7 @@ architecture SYN of ip_agi027_xxxx_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
u_altera_syncram : altera_syncram
......@@ -137,7 +137,7 @@ begin
rdaddr <= to_integer(unsigned(rdaddress));
wraddr <= to_integer(unsigned(wraddress));
u_mem : entity work.ip_agi027_xxxx_simple_dual_port_ram_single_clock
u_mem : entity work.ip_agi027_1e1v_simple_dual_port_ram_single_clock
generic map (
DATA_WIDTH => g_dat_w,
ADDR_WIDTH => g_adr_w
......
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.ip → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.ip
+ 2
− 2
View file @ 87fdde83
......@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_agi027_xxxx_ram_rw_rw</ipxact:library>
<ipxact:library>ip_agi027_1e1v_ram_rw_rw</ipxact:library>
<ipxact:name>ram_2port_0</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
<ipxact:busInterfaces>
......@@ -609,7 +609,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_agi027_xxxx_ram_rw_rw</ipxact:library>
<ipxact:library>ip_agi027_1e1v_ram_rw_rw</ipxact:library>
<ipxact:name>ram_2port</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
</altera:entity_info>
......
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd
+ 6
− 6
View file @ 87fdde83
......@@ -23,7 +23,7 @@
-- RadioHDL wrapper / Instantiate RAM IP with generics
-- Description:
-- Copied component declaration and instance example from
-- generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_rw_rw_ram_2port_2040_uxwhvmq.vhd
-- generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_rw_rw_ram_2port_2040_uxwhvmq.vhd
-- Remark:
-- The outcome of the synthesis is that the parameter
-- read_during_write_mode_mixed_ports cannot be set to the
......@@ -37,7 +37,7 @@ use technology_lib.technology_pkg.all;
library altera_lnsim;
use altera_lnsim.altera_lnsim_components.all;
entity ip_agi027_xxxx_ram_rw_rw is
entity ip_agi027_1e1v_ram_rw_rw is
generic (
g_inferred : boolean := false;
g_adr_w : natural := 5;
......@@ -57,9 +57,9 @@ entity ip_agi027_xxxx_ram_rw_rw is
q_a : out std_logic_vector(g_dat_w - 1 downto 0);
q_b : out std_logic_vector(g_dat_w - 1 downto 0)
);
end ip_agi027_xxxx_ram_rw_rw;
end ip_agi027_1e1v_ram_rw_rw;
architecture SYN of ip_agi027_xxxx_ram_rw_rw is
architecture SYN of ip_agi027_1e1v_ram_rw_rw is
constant c_outdata_reg : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
component altera_syncram
......@@ -117,7 +117,7 @@ architecture SYN of ip_agi027_xxxx_ram_rw_rw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
begin
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_rw_rw : read latency must be 1 (default) or 2" severity FAILURE;
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_rw_rw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
u_altera_syncram : altera_syncram
......@@ -170,7 +170,7 @@ begin
addr_a <= to_integer(unsigned(address_a));
addr_b <= to_integer(unsigned(address_b));
u_mem : entity work.ip_agi027_xxxx_true_dual_port_ram_single_clock
u_mem : entity work.ip_agi027_1e1v_true_dual_port_ram_single_clock
generic map (
DATA_WIDTH => g_dat_w,
ADDR_WIDTH => g_adr_w
......
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_dual_clock.vhd
+ 3
− 3
View file @ 87fdde83
......@@ -34,7 +34,7 @@
library ieee;
use ieee.std_logic_1164.all;
entity ip_agi027_xxxx_simple_dual_port_ram_dual_clock is
entity ip_agi027_1e1v_simple_dual_port_ram_dual_clock is
generic
(
DATA_WIDTH : natural := 8;
......@@ -50,9 +50,9 @@ entity ip_agi027_xxxx_simple_dual_port_ram_dual_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
end ip_agi027_xxxx_simple_dual_port_ram_dual_clock;
end ip_agi027_1e1v_simple_dual_port_ram_dual_clock;
architecture rtl of ip_agi027_xxxx_simple_dual_port_ram_dual_clock is
architecture rtl of ip_agi027_1e1v_simple_dual_port_ram_dual_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
......
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
+ 3
− 3
View file @ 87fdde83
......@@ -34,7 +34,7 @@
library ieee;
use ieee.std_logic_1164.all;
entity ip_agi027_xxxx_simple_dual_port_ram_single_clock is
entity ip_agi027_1e1v_simple_dual_port_ram_single_clock is
generic
(
DATA_WIDTH : natural := 8;
......@@ -49,9 +49,9 @@ entity ip_agi027_xxxx_simple_dual_port_ram_single_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
end ip_agi027_xxxx_simple_dual_port_ram_single_clock;
end ip_agi027_1e1v_simple_dual_port_ram_single_clock;
architecture rtl of ip_agi027_xxxx_simple_dual_port_ram_single_clock is
architecture rtl of ip_agi027_1e1v_simple_dual_port_ram_single_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
......
libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd → libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
+ 3
− 3
View file @ 87fdde83
......@@ -38,7 +38,7 @@
library ieee;
use ieee.std_logic_1164.all;
entity ip_agi027_xxxx_true_dual_port_ram_single_clock is
entity ip_agi027_1e1v_true_dual_port_ram_single_clock is
generic
(
DATA_WIDTH : natural := 8;
......@@ -56,9 +56,9 @@ entity ip_agi027_xxxx_true_dual_port_ram_single_clock is
q_a : out std_logic_vector((DATA_WIDTH - 1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
end ip_agi027_xxxx_true_dual_port_ram_single_clock;
end ip_agi027_1e1v_true_dual_port_ram_single_clock;
architecture rtl of ip_agi027_xxxx_true_dual_port_ram_single_clock is
architecture rtl of ip_agi027_1e1v_true_dual_port_ram_single_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
......
libraries/technology/ip_agi027_xxxx/reset_release/README.txt → libraries/technology/ip_agi027_1e1v/reset_release/README.txt
+ 21
− 21
View file @ 87fdde83
......@@ -19,7 +19,7 @@
###############################################################################
README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/reset_release
README.txt for $HDL_WORK/libraries/technology/ip_agi027_1e1v/reset_release
VERSION 01 - 20240105
Contents:
......@@ -47,8 +47,8 @@ Contents:
The generated IPs are not kept in git repository, only the ip source files:
ip_agi027_xxxx_reset_release_ci.ip
ip_agi027_xxxx_reset_release_ri.ip
ip_agi027_1e1v_reset_release_ci.ip
ip_agi027_1e1v_reset_release_ri.ip
Therefore first the IP needs to be generated using:
......@@ -73,8 +73,8 @@ Contents:
The QIP file:
ip_agi027_xxxx_reset_release_ci.qip
ip_agi027_xxxx_reset_release_ri.qip
ip_agi027_1e1v_reset_release_ci.qip
ip_agi027_1e1v_reset_release_ri.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
......@@ -120,8 +120,8 @@ c) Choose between using or not using a separate library in altera_libraries:
So when the same source files are used by the IPs (no hashes) use:
hdl_lib_name = ip_agi027_xxxx_<lib_name>
hdl_library_clause_name = ip_agi027_xxxx_<lib_name>_lib
hdl_lib_name = ip_agi027_1e1v_<lib_name>
hdl_library_clause_name = ip_agi027_1e1v_<lib_name>_lib
Therefore the compile_ip.tcl has to vmap IP specific libraries, compile all
IP source files into these libraries and to compile the sim source files:
......@@ -129,13 +129,13 @@ c) Choose between using or not using a separate library in altera_libraries:
#repeat for all ip specific libraries
vmap <lib_name>_<ip_specific>
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>"
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_<ip_name>"
#repeat for all IP source files. When multiple same files? Only one IP source file is
#needed for compilation into those libraries
vlog -sv <ip_specific>.sv -work <ip_specific>
#Repeat for all IPs
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>/sim"
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_<ip_name>/sim"
vcom "$IP_DIR/<ip_name>.vhd"
II) Separate library
......@@ -144,34 +144,34 @@ c) Choose between using or not using a separate library in altera_libraries:
preferable to move the library to the altera_libraries, use generated IP
specific library clause name and IP specific lib uses sim.
The generated ip_agi027_xxxx_<lib_name>.vhd uses an IP specific library name.
The generated ip_agi027_1e1v_<lib_name>.vhd uses an IP specific library name.
Therefore the hdllib.cfg uses the IP specific part as library clause name and,
in addition, uses lib uses sim to make it known:
hdl_lib_name = ip_agi027_xxxx_<lib_name>
hdl_library_clause_name = ip_agi027_xxxx_<lib_name>_<ip_specific>
hdl_lib_uses_sim = ip_agi027_xxxx_<ip_specific>
hdl_lib_name = ip_agi027_1e1v_<lib_name>
hdl_library_clause_name = ip_agi027_1e1v_<lib_name>_<ip_specific>
hdl_lib_uses_sim = ip_agi027_1e1v_<ip_specific>
Therefore the compile_ip.tcl has only to compile the sim source files:
#Repeat for all IPs
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>/sim"
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_<ip_name>/sim"
vcom "$IP_DIR/<ip_name>.vhd"
#This means:
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ci/sim"
vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ci.vhd"
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ri/sim"
vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ri.vhd"
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ci/sim"
vcom "$IP_DIR/ip_agi027_1e1v_reset_release_ci.vhd"
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ri/sim"
vcom "$IP_DIR/ip_agi027_1e1v_reset_release_ri.vhd"
Therefore the altera_libraries hdllib.cfg uses ip specific part as library clause
name and assign the altera_libraries compile_ip.tcl to 'modelsim_compile_ip_files =':
hdl_lib_name = ip_agi027_xxxx_<ip_specific>
hdl_lib_name = ip_agi027_1e1v_<ip_specific>
hdl_library_clause_name = <ip_specific>
modelsim_compile_ip_files =
$HDL_WORK/libraries/technology/ip_agi027_xxxx/altera_libraries/<ip_specific>/compile_ip.tcl
$HDL_WORK/libraries/technology/ip_agi027_1e1v/altera_libraries/<ip_specific>/compile_ip.tcl
Therefore the altera_libraries compile.tcl has to vmap IP specific libraries, compile all
IP source files into these 'shared' libraries:
......@@ -179,7 +179,7 @@ c) Choose between using or not using a separate library in altera_libraries:
#repeat for all ip specific libraries
vmap <lib_name>_<ip_specific>
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>"
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_<ip_name>"
#repeat for all IP source files. When multiple same files? Only one IP source file is
#needed for compilation into those libraries
vlog -sv <ip_specific>.sv -work <ip_specific>
......
libraries/technology/ip_agi027_xxxx/reset_release/compile_ip.tcl → libraries/technology/ip_agi027_1e1v/reset_release/compile_ip.tcl
+ 8
− 8
View file @ 87fdde83
......@@ -36,15 +36,15 @@ vlib ./work/ ;# Assume library work already exist
vmap altera_s10_user_rst_clkgate_1945 ./work/
# Compile SystemVerilog file for altera_s10_user_rst_clkgate_1945. Read remark.
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ci"
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ci"
vlog -sv "$IP_DIR/altera_s10_user_rst_clkgate_1945/sim/altera_s10_user_rst_clkgate.sv" -work altera_s10_user_rst_clkgate_1945
#set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ri"
#set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ri"
# vlog -sv "$IP_DIR/altera_s10_user_rst_clkgate_1945/sim/altera_s10_user_rst_clkgate.sv" -work altera_s10_user_rst_clkgate_1945
# Compile VHDL file for ip_agi027_xxxx_reset_release_ci
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ci/sim"
vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ci.vhd"
# Compile VHDL file for ip_agi027_1e1v_reset_release_ci
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ci/sim"
vcom "$IP_DIR/ip_agi027_1e1v_reset_release_ci.vhd"
# Compile VHDL file for ip_agi027_xxxx_reset_release_ri
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ri/sim"
vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ri.vhd"
# Compile VHDL file for ip_agi027_1e1v_reset_release_ri
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ri/sim"
vcom "$IP_DIR/ip_agi027_1e1v_reset_release_ri.vhd"
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