Merge branch 'master' of git.astron.nl:desp/hdl

libraries/dsp/st/src/vhdl/st_histogram.vhd

@@ -137,10 +137,10 @@ ARCHITECTURE rtl OF st_histogram IS
   -- snk_in_reg_arr
   -------------------------------------------------------------------------------
   CONSTANT c_ram_rd_wr_latency : NATURAL := 3; -- RAM read,incr,write cycle latency
-  CONSTANT c_shiftreg_depth    : NATURAL := c_ram_rd_wr_latency;
+  CONSTANT c_shiftreg_depth    : NATURAL := c_ram_rd_wr_latency+1;
 
-  SIGNAL snk_in_reg_arr     : t_dp_sosi_arr(c_shiftreg_depth DOWNTO 0);
-  SIGNAL nxt_snk_in_reg_arr : t_dp_sosi_arr(c_shiftreg_depth DOWNTO 0);
+  SIGNAL snk_in_reg_arr     : t_dp_sosi_arr(c_shiftreg_depth-1 DOWNTO 0);
+  SIGNAL nxt_snk_in_reg_arr : t_dp_sosi_arr(c_shiftreg_depth-1 DOWNTO 0);
   SIGNAL snk_in_reg         : t_dp_sosi;
 
   -------------------------------------------------------------------------------
@@ -250,11 +250,9 @@ BEGIN
   -------------------------------------------------------------------------------
   p_nxt_snk_in_reg_arr: PROCESS(snk_in, snk_in_data, snk_in_reg_arr) IS
   BEGIN
-    nxt_snk_in_reg_arr <= snk_in_reg_arr;
-    nxt_snk_in_reg_arr(3).valid <= '0';
-    --FOR i IN 0 TO c_shiftreg_depth-1 LOOP
-    --  nxt_snk_in_reg_arr(i) <= c_dp_sosi_rst;
-    --END LOOP;
+    FOR i IN 0 TO c_shiftreg_depth-1 LOOP
+      nxt_snk_in_reg_arr(i) <= c_dp_sosi_rst;
+    END LOOP;
 
     IF snk_in.valid='1' THEN
       -- The base function is a shift register