IP for 16GB DDR3 So-Dimm modules added

libraries/technology/ddr/tech_ddr_pkg.vhd

@@ -69,13 +69,14 @@ PACKAGE tech_ddr_pkg IS
   
   --                                                                                                    a   a                               cs cs
   --                                                                 name    mts   master rank      a   row col ba dq  dqs dm dbi bg ck cke w  w_w  odt term rsl rsl_w cqd burst burst_w
-  CONSTANT c_tech_ddr3_max                        : t_c_tech_ddr := ("none",  800,  TRUE, "DUAL  ", 16, 16, 10, 3, 64, 8,  8, 0,  0, 2, 2,  2, 1,   2,  14,  4,  2,    4,  64,   7);  -- maximum ranges for record field definitions
+  CONSTANT c_tech_ddr3_max                        : t_c_tech_ddr := ("none",  800,  TRUE, "DUAL  ", 16, 16, 11, 3, 64, 8,  8, 0,  0, 2, 2,  2, 1,   2,  14,  4,  2,    4,  64,   7);  -- maximum ranges for record field definitions
   
   CONSTANT c_tech_ddr3_sim_8k                     : t_c_tech_ddr := ("DDR3",  800,  TRUE, "DUAL  ", 10,  1, 10, 3, 64, 8,  8, 0,  0, 2, 2,  2, 1,   2,  14,  4,  2,    4,  64,   7);  -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
   CONSTANT c_tech_ddr3_sim_16k                    : t_c_tech_ddr := ("DDR3",  800,  TRUE, "DUAL  ", 10,  2, 10, 3, 64, 8,  8, 0,  0, 2, 2,  2, 1,   2,  14,  4,  2,    4,  64,   7);  -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
   CONSTANT c_tech_ddr3_sim_128k                   : t_c_tech_ddr := ("DDR3",  800,  TRUE, "DUAL  ", 10,  5, 10, 3, 64, 8,  8, 0,  0, 2, 2,  2, 1,   2,  14,  4,  2,    4,  64,   7);  -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
   CONSTANT c_tech_ddr3_sim_1m                     : t_c_tech_ddr := ("DDR3",  800,  TRUE, "DUAL  ", 10,  8, 10, 3, 64, 8,  8, 0,  0, 2, 2,  2, 1,   2,  14,  4,  2,    4,  64,   7);  -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
   
+  CONSTANT c_tech_ddr3_16g_dual_rank_800m         : t_c_tech_ddr := ("DDR3",  800,  TRUE, "DUAL  ", 16, 16, 11, 3, 64, 8,  8, 0,  0, 2, 2,  2, 1,   2,  14,  4,  2,    4,  64,   7);
   CONSTANT c_tech_ddr3_4g_800m_master             : t_c_tech_ddr := ("DDR3",  800,  TRUE, "DUAL  ", 15, 15, 10, 3, 64, 8,  8, 0,  0, 2, 2,  2, 1,   2,  14,  4,  2,    4,  64,   7);
   CONSTANT c_tech_ddr3_4g_800m_slave              : t_c_tech_ddr := ("DDR3",  800, FALSE, "DUAL  ", 15, 15, 10, 3, 64, 8,  8, 0,  0, 2, 2,  2, 1,   2,  14,  4,  2,    4,  64,   7);
   CONSTANT c_tech_ddr3_4g_single_rank_800m_master : t_c_tech_ddr := ("DDR3",  800,  TRUE, "SINGLE", 16, 16, 10, 3, 64, 8,  8, 0,  0, 2, 1,  1, 0,   1,  14,  4,  2,    4,  64,   7);
@@ -161,10 +162,21 @@ PACKAGE tech_ddr_pkg IS
   TYPE t_tech_ddr3_phy_terminationcontrol IS RECORD                                                 -- DDR3 Termination control
     seriesterminationcontrol   : STD_LOGIC_VECTOR(c_tech_ddr3_max.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
     parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr3_max.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
+    pll_mem_clk                : STD_LOGIC;
+    pll_write_clk              : STD_LOGIC;
+    pll_write_clk_pre_phy_clk  : STD_LOGIC;
+    pll_addr_cmd_clk           : STD_LOGIC;
+    pll_locked                 : STD_LOGIC;
+    pll_avl_clk                : STD_LOGIC;
+    pll_config_clk             : STD_LOGIC;
+    dll_delayctrl              : STD_LOGIC_VECTOR(5 DOWNTO 0);
+    afi_clk                    : STD_LOGIC;
+    afi_half_clk               : STD_LOGIC;
+    afi_reset_n                : STD_LOGIC;
   END RECORD;
 
-  CONSTANT c_tech_ddr3_phy_terminationcontrol_x   : t_tech_ddr3_phy_terminationcontrol := ((OTHERS=>'X'), (OTHERS=>'X'));
-  CONSTANT c_tech_ddr3_phy_terminationcontrol_rst : t_tech_ddr3_phy_terminationcontrol := ((OTHERS=>'0'), (OTHERS=>'0'));
+  CONSTANT c_tech_ddr3_phy_terminationcontrol_x   : t_tech_ddr3_phy_terminationcontrol := ((OTHERS=>'X'), (OTHERS=>'X'),'X','X','X','X','X','X','X', (OTHERS=>'X'), 'X', 'X', 'X');
+  CONSTANT c_tech_ddr3_phy_terminationcontrol_rst : t_tech_ddr3_phy_terminationcontrol := ((OTHERS=>'0'), (OTHERS=>'0'),'0','0','0','0','0','0','0', (OTHERS=>'0'), '0', '0', '0');
 
   CONSTANT c_tech_ddr3_phy_in_x     : t_tech_ddr3_phy_in := ('X', 'X', 'X');
   CONSTANT c_tech_ddr4_phy_in_x     : t_tech_ddr4_phy_in := ('X', 'X');