Added g_slave_enable_arr to support not connected MM slaves.

libraries/base/mm/src/vhdl/mm_bus.vhd

@@ -29,6 +29,7 @@
 --   - slaves that do not need flow control
 --                                    
 --                                     FOR g_nof_slaves:
+--                             g_slave_enable_arr
 --                             g_waitrequest_arr
 --                             g_rd_latency_arr 
 --                              |          |
@@ -114,6 +115,7 @@ ENTITY mm_bus IS
     g_base_arr            : t_nat_natural_arr;  -- Address base per slave
     g_width_arr           : t_nat_natural_arr;  -- Address width per slave
     g_rd_latency_arr      : t_nat_natural_arr;  -- Read latency per slave
+    g_slave_enable_arr    : t_nat_boolean_arr;  -- Use FALSE for not connected slaves, else TRUE
     g_waitrequest_arr     : t_nat_boolean_arr;  -- Enable waitrequest flow control per slave, else fixed '0'
     g_pipeline_mosi       : BOOLEAN := FALSE;   -- Pipeline MM access (wr, rd)
     g_pipeline_miso_rdval : BOOLEAN := FALSE;   -- Pipeline MM read (rdval)
@@ -162,7 +164,7 @@ BEGIN
     -- Rewire not connected slaves and slave that do not need mosi flow control via miso.waitrequest
     u_slave_enable : ENTITY work.mm_slave_enable
     GENERIC MAP (
-      g_enable       => TRUE,
+      g_enable       => g_slave_enable_arr(I),
       g_waitrequest  => g_waitrequest_arr(I),
       g_rd_latency   => g_rd_latency_arr(I)
     )

libraries/base/mm/tb/vhdl/tb_mm_bus.vhd

@@ -79,6 +79,7 @@ ARCHITECTURE tb OF tb_mm_bus IS
   CONSTANT c_base_arr        : t_nat_natural_arr := array_init(g_base_offset, g_nof_slaves, c_slave_span);  -- Address base per slave
   CONSTANT c_width_arr       : t_nat_natural_arr := array_init(    g_width_w, g_nof_slaves);                -- Address width per slave
   CONSTANT c_rd_latency_arr  : t_nat_natural_arr := array_init( g_rd_latency, g_nof_slaves);                -- Read latency per slave
+  CONSTANT c_slave_enable_arr: t_nat_boolean_arr := array_init(         TRUE, g_nof_slaves);                -- TRUE for connected slaves
   CONSTANT c_waitrequest_arr : t_nat_boolean_arr := array_init(g_waitrequest, g_nof_slaves);                -- Flow control per slave
   
   CONSTANT c_bus_pipelining      : BOOLEAN := g_pipeline_mosi OR g_pipeline_miso_rdval OR g_pipeline_miso_wait;
@@ -194,6 +195,7 @@ BEGIN
     g_base_arr            => c_base_arr,
     g_width_arr           => c_width_arr,
     g_rd_latency_arr      => c_rd_latency_arr,
+    g_slave_enable_arr    => c_slave_enable_arr,
     g_waitrequest_arr     => c_waitrequest_arr,
     g_pipeline_mosi       => g_pipeline_mosi,
     g_pipeline_miso_rdval => g_pipeline_miso_rdval,

libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd

@@ -77,6 +77,7 @@ ARCHITECTURE tb OF tb_mm_master_mux IS
   CONSTANT c_bus_pipeline_miso_wait  : NATURAL := sel_a_b(g_pipeline_bus_miso_wait, 1, 0);
   CONSTANT c_ram_rd_latency          : NATURAL := 1; 
   CONSTANT c_ram_rd_latency_arr      : t_nat_natural_arr := array_init(c_ram_rd_latency, g_nof_masters);
+  CONSTANT c_slave_enable_arr        : t_nat_boolean_arr := array_init(TRUE, g_nof_masters);
   CONSTANT c_waitrequest_arr         : t_nat_boolean_arr := array_init(g_waitrequest, g_nof_masters);
   
   CONSTANT c_read_latency    : NATURAL := c_bus_pipeline_mosi + c_ram_rd_latency + c_bus_pipeline_miso_rdval;
@@ -162,6 +163,7 @@ BEGIN
     g_base_arr            => g_base_arr,
     g_width_arr           => g_width_arr,
     g_rd_latency_arr      => c_ram_rd_latency_arr,
+    g_slave_enable_arr    => c_slave_enable_arr,
     g_waitrequest_arr     => c_waitrequest_arr,
     g_pipeline_mosi       => g_pipeline_bus_mosi,
     g_pipeline_miso_rdval => g_pipeline_bus_miso_rdval,