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Commit 846aff97 authored by Zanting's avatar Zanting
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Added revision unb1_test_16g_MB_I

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boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg 0 → 100644
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hdl_lib_name = unb1_test_ddr_16g_MB_I
hdl_library_clause_name = unb1_test_ddr_16g_MB_I_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv
synth_files =
unb1_test_ddr_16g_MB_I.vhd
test_bench_files =
tb_unb1_test_ddr_16g_MB_I.vhd
modelsim_copy_files =
../../src/hex hex
synth_top_level_entity =
quartus_copy_files =
../../quartus/qsys_unb1_test.qsys .
../../src/hex hex
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_16g_MB_I_pins.tcl
quartus/unb1_test_ddr_16g_MB_I_pins_constraints.tcl
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl 0 → 100644
+ 29
− 0
View file @ 846aff97
###############################################################################
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins_constraints.tcl 0 → 100644
+ 520
− 0
View file @ 846aff97
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[15] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[15] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cs_n[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cs_n[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.we_n -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.we_n -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cke[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cke[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.odt[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.odt[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD 1.5V -to MB_I_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|pll0|upll_memphy|auto_generated|clk[1]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|pll0|upll_memphy|auto_generated|clk[2]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|pll0|upll_memphy|auto_generated|clk[3]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|pll0|upll_memphy|auto_generated|clk[5]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|pll0|upll_memphy|auto_generated|clk[6]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|ureset|phy_reset_n" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[1]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[2]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[3]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[4]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[5]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[6]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[7]" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT ON -to "u_revision|\\gen_ddr_stream_16g_MB_I:u_ddr_stream_16g_MB_I|u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\\gen_ip:gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800:u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800|ip_stratixiv_ddr3_uphy_16g_dual_rank_800_inst|pll0|upll_memphy|auto_generated|pll1" -tag __ip_stratixiv_ddr3_uphy_16g_dual_rank_800_p0
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name UNIPHY_TEMP_VER_CODE 509668869
\ No newline at end of file
boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd 0 → 100644
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− 0
View file @ 846aff97
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Test bench for unb1_test_ddr_16g_MB_I.
-- Description: see tb_unb1_test
LIBRARY IEEE, unb1_test_lib;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_unb1_test_ddr_16g_MB_I IS
END tb_unb1_test_ddr_16g_MB_I;
ARCHITECTURE tb OF tb_unb1_test_ddr_16g_MB_I IS
BEGIN
u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
GENERIC MAP (
g_design_name => "unb1_test_ddr_16g_MB_I",
--g_sim_node_nr => 7 -- BN3
g_sim_node_nr => 0 --FN0
);
END tb;
boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd 0 → 100644
+ 115
− 0
View file @ 846aff97
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY unb1_test_ddr_16g_MB_I IS
GENERIC (
g_design_name : STRING := "unb1_test_ddr_16g_MB_I"; -- use revision name = entity name = design name
g_design_note : STRING := "Test with 16GB MB_I DDR3";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; -- FN0
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
SENS_SD : INOUT STD_LOGIC;
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC;
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
);
END unb1_test_ddr_16g_MB_I;
ARCHITECTURE str OF unb1_test_ddr_16g_MB_I IS
BEGIN
u_revision : ENTITY unb1_test_lib.unb1_test
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn
)
PORT MAP (
-- GENERAL
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- I2C Interface to Sensors
sens_sc => sens_sc,
sens_sd => sens_sd,
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- SO-DIMM Memory Bank I
MB_I_IN => MB_I_IN,
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU
);
END str;
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