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Commit 8417490f authored by Priest's avatar Priest
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Added support for 8 nodes (4 front, 4 back)

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applications/stagiair/libraries/terminal/tb/vhdl/tb_terminal_node.vhd
+ 242
− 185
View file @ 8417490f
...@@ -23,12 +23,12 @@ USE IEEE.STD_LOGIC_1164.ALL; ...@@ -23,12 +23,12 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL; USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL; USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; USE unb1_board_lib.tb_unb1_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL; USE mm_lib.mm_file_unb_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL; USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
ENTITY tb_terminal_node IS ENTITY tb_terminal_node IS
END tb_terminal_node; END tb_terminal_node;
...@@ -37,16 +37,20 @@ ARCHITECTURE t_bench OF tb_terminal_node IS ...@@ -37,16 +37,20 @@ ARCHITECTURE t_bench OF tb_terminal_node IS
-- Clocks -- Clocks
CONSTANT c_mm_clk_period : TIME := 20 ns; -- 100 ps; CONSTANT c_mm_clk_period : TIME := 20 ns; -- 100 ps;
CONSTANT c_dp_clk_period : TIME := 5 ns; CONSTANT c_dp_clk_period : TIME := 5 ns;
CONSTANT c_tr_clk_period : TIME := 6.4 ns; CONSTANT c_tr_clk_period : TIME := 6400 ps;
CONSTANT c_cal_rec_clk_period : TIME := 25 ns; CONSTANT c_cal_rec_clk_period : TIME := 25 ns;
CONSTANT c_sim : BOOLEAN := TRUE; CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_sim_level : NATURAL := 1; CONSTANT c_sim_level : NATURAL := 1;
CONSTANT c_nof_nodes : NATURAL := 2; CONSTANT c_nof_fn : NATURAL := 4;
CONSTANT c_nof_bn : NATURAL := 4;
CONSTANT c_nof_nodes : NATURAL := c_nof_fn + c_nof_bn;
CONSTANT c_ena_mesh_reorder : BOOLEAN := TRUE;
CONSTANT c_chip_id_w : NATURAL := 3;
TYPE t_fn_bn_arr IS ARRAY (INTEGER RANGE<>) OF STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); TYPE t_mesh_arr IS ARRAY (0 TO c_nof_nodes-1) OF STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
TYPE t_fn_bn_2arr IS ARRAY (INTEGER RANGE<>) OF t_fn_bn_arr(7 DOWNTO 0);
-- Clock signals -- Clock signals
SIGNAL dp_clk : STD_LOGIC := '0'; SIGNAL dp_clk : STD_LOGIC := '0';
...@@ -57,58 +61,40 @@ ARCHITECTURE t_bench OF tb_terminal_node IS ...@@ -57,58 +61,40 @@ ARCHITECTURE t_bench OF tb_terminal_node IS
SIGNAL tr_clk : STD_LOGIC := '0'; SIGNAL tr_clk : STD_LOGIC := '0';
SIGNAL cal_rec_clk : STD_LOGIC := '0'; SIGNAL cal_rec_clk : STD_LOGIC := '0';
-- 2D array of the FN_BN_0 to FN_BN_3 signals
-- Set TX and RX in different arrays?
-- SIGNAL fn_bn_tx_rx_2arr : t_fn_bn_2arr(0 TO c_nof_nodes);
-----------------------------------------------------------------------------
-- FN0 Signals
-----------------------------------------------------------------------------
SIGNAL fn0_bg_reg_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL fn0_bg_reg_ctrl_miso : t_mem_miso;
SIGNAL fn0_bg_ram_data_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL fn0_bg_ram_data_miso : t_mem_miso;
SIGNAL fn0_db_ram_data_buf_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL fn0_db_ram_data_buf_miso : t_mem_miso;
SIGNAL fn0_db_reg_data_buf_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL fn0_db_reg_data_buf_miso : t_mem_miso;
SIGNAL fn0_reg_tr_nonbonded_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL fn0_reg_tr_nonbonded_miso : t_mem_miso;
SIGNAL fn0_reg_diagnostics_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL fn0_reg_diagnostics_miso : t_mem_miso;
SIGNAL fn0_FN_BN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL fn0_FN_BN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL fn0_FN_BN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL fn0_FN_BN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL fn0_FN_BN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL fn0_FN_BN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL fn0_FN_BN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL fn0_FN_BN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- BN0 Signals -- DUT signals
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
SIGNAL bn0_bg_reg_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst; SIGNAL bg_reg_ctrl_mosi_arr : t_mem_mosi_arr(c_nof_nodes-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL bn0_bg_reg_ctrl_miso : t_mem_miso; SIGNAL bg_reg_ctrl_miso_arr : t_mem_miso_arr(c_nof_nodes-1 DOWNTO 0);
SIGNAL bn0_bg_ram_data_mosi : t_mem_mosi := c_mem_mosi_rst; SIGNAL bg_ram_data_mosi_arr : t_mem_mosi_arr(c_nof_nodes-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL bn0_bg_ram_data_miso : t_mem_miso; SIGNAL bg_ram_data_miso_arr : t_mem_miso_arr(c_nof_nodes-1 DOWNTO 0);
SIGNAL bn0_db_ram_data_buf_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL bn0_db_ram_data_buf_miso : t_mem_miso; SIGNAL db_ram_data_buf_mosi_arr : t_mem_mosi_arr(c_nof_nodes-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL bn0_db_reg_data_buf_mosi : t_mem_mosi := c_mem_mosi_rst; SIGNAL db_ram_data_buf_miso_arr : t_mem_miso_arr(c_nof_nodes-1 DOWNTO 0);
SIGNAL bn0_db_reg_data_buf_miso : t_mem_miso; SIGNAL db_reg_data_buf_mosi_arr : t_mem_mosi_arr(c_nof_nodes-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL bn0_reg_tr_nonbonded_mosi : t_mem_mosi := c_mem_mosi_rst; SIGNAL db_reg_data_buf_miso_arr : t_mem_miso_arr(c_nof_nodes-1 DOWNTO 0);
SIGNAL bn0_reg_tr_nonbonded_miso : t_mem_miso;
SIGNAL bn0_reg_diagnostics_mosi : t_mem_mosi := c_mem_mosi_rst; SIGNAL mt_reg_tr_nonbonded_mosi_arr : t_mem_mosi_arr(c_nof_nodes-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL bn0_reg_diagnostics_miso : t_mem_miso; SIGNAL mt_reg_tr_nonbonded_miso_arr : t_mem_miso_arr(c_nof_nodes-1 DOWNTO 0);
SIGNAL mt_reg_diagnostics_mosi_arr : t_mem_mosi_arr(c_nof_nodes-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL bn0_FN_BN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); SIGNAL mt_reg_diagnostics_miso_arr : t_mem_miso_arr(c_nof_nodes-1 DOWNTO 0);
SIGNAL bn0_FN_BN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL bn0_FN_BN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); SIGNAL FN_BN_0_TX_arr : t_mesh_arr;
SIGNAL bn0_FN_BN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); SIGNAL FN_BN_0_RX_arr : t_mesh_arr;
SIGNAL bn0_FN_BN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); SIGNAL FN_BN_1_TX_arr : t_mesh_arr;
SIGNAL bn0_FN_BN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); SIGNAL FN_BN_1_RX_arr : t_mesh_arr;
SIGNAL bn0_FN_BN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); SIGNAL FN_BN_2_TX_arr : t_mesh_arr;
SIGNAL bn0_FN_BN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); SIGNAL FN_BN_2_RX_arr : t_mesh_arr;
SIGNAL FN_BN_3_TX_arr : t_mesh_arr;
SIGNAL FN_BN_3_RX_arr : t_mesh_arr;
------------------------------------------------------------------------------
-- BN & FN mesh side serial I/O
------------------------------------------------------------------------------
SIGNAL bn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
SIGNAL bn_in_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
SIGNAL fn_in_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
SIGNAL fn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
COMPONENT mm_file COMPONENT mm_file
GENERIC( GENERIC(
...@@ -133,17 +119,21 @@ BEGIN ...@@ -133,17 +119,21 @@ BEGIN
tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2; tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2;
cal_rec_clk <= NOT cal_rec_clk AFTER c_cal_rec_clk_period/2; cal_rec_clk <= NOT cal_rec_clk AFTER c_cal_rec_clk_period/2;
---------------------------------------------------------------------------
dutFN0 : ENTITY work.terminal_node -- Generate front and back nodes
GENERIC MAP( --------------------------------------------------------------------------
gen_fn : FOR FN IN 0 TO c_nof_fn-1 GENERATE
dutFN : ENTITY work.terminal_node
GENERIC MAP
(
g_sim => c_sim, g_sim => c_sim,
g_sim_level => c_sim_level, g_sim_level => c_sim_level,
g_sim_node_nr => 0 g_sim_node_nr => FN
--g_node_type => e_fn --g_node_type => e_fn
) )
PORT MAP( PORT MAP(
-- System -- System
chip_id => "000", -- Front node 0 chip_id => TO_UVEC(FN, c_chip_id_w),
mm_rst => mm_rst, mm_rst => mm_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
dp_rst => dp_rst, dp_rst => dp_rst,
...@@ -153,41 +143,66 @@ BEGIN ...@@ -153,41 +143,66 @@ BEGIN
cal_clk => cal_rec_clk, cal_clk => cal_rec_clk,
-- MM interface -- MM interface
-- Block generator -- Block generator
bg_reg_ctrl_mosi => fn0_bg_reg_ctrl_mosi, bg_reg_ctrl_mosi => bg_reg_ctrl_mosi_arr(FN),
bg_reg_ctrl_miso => fn0_bg_reg_ctrl_miso, bg_reg_ctrl_miso => bg_reg_ctrl_miso_arr(FN),
bg_ram_data_mosi => fn0_bg_ram_data_mosi, bg_ram_data_mosi => bg_ram_data_mosi_arr(FN),
bg_ram_data_miso => fn0_bg_ram_data_miso, bg_ram_data_miso => bg_ram_data_miso_arr(FN),
-- Diag Data buffer -- Diag Data buffer
db_ram_data_buf_mosi => fn0_db_ram_data_buf_mosi, db_ram_data_buf_mosi => db_ram_data_buf_mosi_arr(FN),
db_ram_data_buf_miso => fn0_db_ram_data_buf_miso, db_ram_data_buf_miso => db_ram_data_buf_miso_arr(FN),
db_reg_data_buf_mosi => fn0_db_reg_data_buf_mosi, db_reg_data_buf_mosi => db_reg_data_buf_mosi_arr(FN),
db_reg_data_buf_miso => fn0_db_reg_data_buf_miso, db_reg_data_buf_miso => db_reg_data_buf_miso_arr(FN),
-- Terminal -- Terminal
reg_tr_nonbonded_mosi => fn0_reg_tr_nonbonded_mosi, reg_tr_nonbonded_mosi => mt_reg_tr_nonbonded_mosi_arr(FN),
reg_tr_nonbonded_miso => fn0_reg_tr_nonbonded_miso, reg_tr_nonbonded_miso => mt_reg_tr_nonbonded_miso_arr(FN),
reg_diagnostics_mosi => fn0_reg_diagnostics_mosi, reg_diagnostics_mosi => mt_reg_diagnostics_mosi_arr(FN),
reg_diagnostics_miso => fn0_reg_diagnostics_miso, reg_diagnostics_miso => mt_reg_diagnostics_miso_arr(FN),
-- Mesh Serial I/O -- Mesh Serial I/O
FN_BN_0_TX => fn0_FN_BN_0_TX, FN_BN_0_TX => FN_BN_0_TX_arr(FN),
FN_BN_0_RX => fn0_FN_BN_0_RX, FN_BN_0_RX => FN_BN_0_RX_arr(FN),
FN_BN_1_TX => fn0_FN_BN_1_TX, FN_BN_1_TX => FN_BN_1_TX_arr(FN),
FN_BN_1_RX => fn0_FN_BN_1_RX, FN_BN_1_RX => FN_BN_1_RX_arr(FN),
FN_BN_2_TX => fn0_FN_BN_2_TX, FN_BN_2_TX => FN_BN_2_TX_arr(FN),
FN_BN_2_RX => fn0_FN_BN_2_RX, FN_BN_2_RX => FN_BN_2_RX_arr(FN),
FN_BN_3_TX => fn0_FN_BN_3_TX, FN_BN_3_TX => FN_BN_3_TX_arr(FN),
FN_BN_3_RX => fn0_FN_BN_3_RX FN_BN_3_RX => FN_BN_3_RX_arr(FN)
); );
dutBN0 : ENTITY work.terminal_node -- Use mesh_io block to create 3arr format for the mesh model.
u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
GENERIC MAP ( GENERIC MAP (
g_bus_w => c_unb1_board_tr_mesh.bus_w
)
PORT MAP (
tx_serial_2arr => fn_in_mesh_serial_3arr(FN),
rx_serial_2arr => fn_out_mesh_serial_3arr(FN),
-- Serial I/O
FN_BN_0_TX => FN_BN_0_RX_arr(FN),
FN_BN_0_RX => FN_BN_0_TX_arr(FN),
FN_BN_1_TX => FN_BN_1_RX_arr(FN),
FN_BN_1_RX => FN_BN_1_TX_arr(FN),
FN_BN_2_TX => FN_BN_2_RX_arr(FN),
FN_BN_2_RX => FN_BN_2_TX_arr(FN),
FN_BN_3_TX => FN_BN_3_RX_arr(FN),
FN_BN_3_RX => FN_BN_3_TX_arr(FN)
);
END GENERATE;
-- Back nodes
gen_bn : FOR BN IN 0 TO c_nof_bn-1 GENERATE
dutBN : ENTITY work.terminal_node
GENERIC MAP
(
g_sim => c_sim, g_sim => c_sim,
g_sim_level => c_sim_level, g_sim_level => c_sim_level,
g_sim_node_nr => 1 g_sim_node_nr => BN
--g_node_type => e_bn --g_node_type => e_bn
) )
PORT MAP( PORT MAP(
-- System -- System
chip_id => "100", -- Back node 0 chip_id => TO_UVEC(BN + 4, c_chip_id_w),
mm_rst => mm_rst, mm_rst => mm_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
dp_rst => dp_rst, dp_rst => dp_rst,
...@@ -197,44 +212,78 @@ BEGIN ...@@ -197,44 +212,78 @@ BEGIN
cal_clk => cal_rec_clk, cal_clk => cal_rec_clk,
-- MM interface -- MM interface
-- Block generator -- Block generator
bg_reg_ctrl_mosi => bn0_bg_reg_ctrl_mosi, bg_reg_ctrl_mosi => bg_reg_ctrl_mosi_arr(BN+c_nof_fn),
bg_reg_ctrl_miso => bn0_bg_reg_ctrl_miso, bg_reg_ctrl_miso => bg_reg_ctrl_miso_arr(BN+c_nof_fn),
bg_ram_data_mosi => bn0_bg_ram_data_mosi, bg_ram_data_mosi => bg_ram_data_mosi_arr(BN+c_nof_fn),
bg_ram_data_miso => bn0_bg_ram_data_miso, bg_ram_data_miso => bg_ram_data_miso_arr(BN+c_nof_fn),
-- Diag Data buffer -- Diag Data buffer
db_ram_data_buf_mosi => bn0_db_ram_data_buf_mosi, db_ram_data_buf_mosi => db_ram_data_buf_mosi_arr(BN+c_nof_fn),
db_ram_data_buf_miso => bn0_db_ram_data_buf_miso, db_ram_data_buf_miso => db_ram_data_buf_miso_arr(BN+c_nof_fn),
db_reg_data_buf_mosi => bn0_db_reg_data_buf_mosi, db_reg_data_buf_mosi => db_reg_data_buf_mosi_arr(BN+c_nof_fn),
db_reg_data_buf_miso => bn0_db_reg_data_buf_miso, db_reg_data_buf_miso => db_reg_data_buf_miso_arr(BN+c_nof_fn),
-- Terminal -- Terminal
reg_tr_nonbonded_mosi => bn0_reg_tr_nonbonded_mosi, reg_tr_nonbonded_mosi => mt_reg_tr_nonbonded_mosi_arr(BN+c_nof_fn),
reg_tr_nonbonded_miso => bn0_reg_tr_nonbonded_miso, reg_tr_nonbonded_miso => mt_reg_tr_nonbonded_miso_arr(BN+c_nof_fn),
reg_diagnostics_mosi => bn0_reg_diagnostics_mosi, reg_diagnostics_mosi => mt_reg_diagnostics_mosi_arr(BN+c_nof_fn),
reg_diagnostics_miso => bn0_reg_diagnostics_miso, reg_diagnostics_miso => mt_reg_diagnostics_miso_arr(BN+c_nof_fn),
-- Mesh Serial I/O -- Mesh Serial I/O
FN_BN_0_TX => bn0_FN_BN_0_TX, FN_BN_0_TX => FN_BN_0_TX_arr(BN+c_nof_fn),
FN_BN_0_RX => bn0_FN_BN_0_RX, FN_BN_0_RX => FN_BN_0_RX_arr(BN+c_nof_fn),
FN_BN_1_TX => bn0_FN_BN_1_TX, FN_BN_1_TX => FN_BN_1_TX_arr(BN+c_nof_fn),
FN_BN_1_RX => bn0_FN_BN_1_RX, FN_BN_1_RX => FN_BN_1_RX_arr(BN+c_nof_fn),
FN_BN_2_TX => bn0_FN_BN_2_TX, FN_BN_2_TX => FN_BN_2_TX_arr(BN+c_nof_fn),
FN_BN_2_RX => bn0_FN_BN_2_RX, FN_BN_2_RX => FN_BN_2_RX_arr(BN+c_nof_fn),
FN_BN_3_TX => bn0_FN_BN_3_TX, FN_BN_3_TX => FN_BN_3_TX_arr(BN+c_nof_fn),
FN_BN_3_RX => bn0_FN_BN_3_RX FN_BN_3_RX => FN_BN_3_RX_arr(BN+c_nof_fn)
);
-- Use mesh_io block to create 3arr format for the mesh model.
u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
GENERIC MAP (
g_bus_w => c_unb1_board_tr_mesh.bus_w
)
PORT MAP (
tx_serial_2arr => bn_in_mesh_serial_3arr(BN),
rx_serial_2arr => bn_out_mesh_serial_3arr(BN),
-- Serial I/O
FN_BN_0_TX => FN_BN_0_RX_arr(BN+c_nof_fn),
FN_BN_0_RX => FN_BN_0_TX_arr(BN+c_nof_fn),
FN_BN_1_TX => FN_BN_1_RX_arr(BN+c_nof_fn),
FN_BN_1_RX => FN_BN_1_TX_arr(BN+c_nof_fn),
FN_BN_2_TX => FN_BN_2_RX_arr(BN+c_nof_fn),
FN_BN_2_RX => FN_BN_2_TX_arr(BN+c_nof_fn),
FN_BN_3_TX => FN_BN_3_RX_arr(BN+c_nof_fn),
FN_BN_3_RX => FN_BN_3_TX_arr(BN+c_nof_fn)
); );
END GENERATE;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- Link the TX and RX's together -- Link the TX and RX's together
-------------------------------------------------------------------------- --------------------------------------------------------------------------
fn0_FN_BN_0_RX <= bn0_FN_BN_0_TX;
fn0_FN_BN_1_RX <= bn0_FN_BN_1_TX; -- Direct interconnect BN0<->FN0.
fn0_FN_BN_2_RX <= bn0_FN_BN_2_TX; no_mesh : IF c_nof_bn=1 AND c_nof_fn=1 GENERATE
fn0_FN_BN_3_RX <= bn0_FN_BN_3_TX; fn_in_mesh_serial_3arr(0) <= bn_out_mesh_serial_3arr(0);
bn0_FN_BN_0_RX <= fn0_FN_BN_0_TX; bn_in_mesh_serial_3arr(0) <= fn_out_mesh_serial_3arr(0);
bn0_FN_BN_1_RX <= fn0_FN_BN_1_TX; END GENERATE;
bn0_FN_BN_2_RX <= fn0_FN_BN_2_TX;
bn0_FN_BN_3_RX <= fn0_FN_BN_3_TX; -- Mesh model
--fn_bn_tx_rx_2arr(0)(1) <= fn_bn_tx_rx_2arr(1)(0); -- FN0:FN_BN_0_RX <= BN0:FN_BN_0_TX gen_mesh : IF c_nof_bn>1 OR c_nof_fn>1 GENERATE
--fn_bn_tx_rx_2arr(1)(1) <= fn_bn_tx_rx_2arr(0)(0); -- BN0:FN_BN_0_RX <= FN0:FN_BN_0_TX u_mesh_model_serial : ENTITY unb1_board_lib.unb1_board_mesh_model_sl
GENERIC MAP(
g_reorder => c_ena_mesh_reorder
)
PORT MAP (
-- FN to BN
fn_tx_sl_3arr => fn_out_mesh_serial_3arr,
bn_rx_sl_3arr => bn_in_mesh_serial_3arr,
-- BN to FN
bn_tx_sl_3arr => bn_out_mesh_serial_3arr,
fn_rx_sl_3arr => fn_in_mesh_serial_3arr
);
END GENERATE;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get -- Procedure that polls a sim control file that can be used to e.g. get
...@@ -242,30 +291,38 @@ BEGIN ...@@ -242,30 +291,38 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat"); mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
u_mm_file_fn0_bg_ram_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG") -- Front nodes
PORT MAP(mm_rst, mm_clk, fn0_bg_ram_data_mosi, fn0_bg_ram_data_miso); gen_mm_fn : FOR i IN 0 TO c_nof_fn-1 GENERATE
u_mm_file_fn0_bg_reg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
PORT MAP(mm_rst, mm_clk, fn0_bg_reg_ctrl_mosi, fn0_bg_reg_ctrl_miso); u_mm_file_bg_ram_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "FN") & "RAM_DIAG_BG")
u_mm_file_fn0_db_ram_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER") PORT MAP(mm_rst, mm_clk, bg_ram_data_mosi_arr(i), bg_ram_data_miso_arr(i));
PORT MAP(mm_rst, mm_clk, fn0_db_ram_data_buf_mosi, fn0_db_ram_data_buf_miso); u_mm_file_bg_reg_diag : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "FN") & "REG_DIAG_BG")
u_mm_file_fn0_db_reg_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER") PORT MAP(mm_rst, mm_clk, bg_reg_ctrl_mosi_arr(i), bg_reg_ctrl_miso_arr(i));
PORT MAP(mm_rst, mm_clk, fn0_db_reg_data_buf_mosi, fn0_db_reg_data_buf_miso); u_mm_file_db_ram_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "FN") & "RAM_DIAG_DATA_BUFFER")
u_mm_file_fn0_tm_tr_nonbo : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_TR_NONBONDED") PORT MAP(mm_rst, mm_clk, db_ram_data_buf_mosi_arr(i), db_ram_data_buf_miso_arr(i));
PORT MAP(mm_rst, mm_clk, fn0_reg_tr_nonbonded_mosi, fn0_reg_tr_nonbonded_miso); u_mm_file_db_reg_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "FN") & "REG_DIAG_DATA_BUFFER")
u_mm_file_fn0_tm_reg_diag: mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAGNOSTICS_MESH") PORT MAP(mm_rst, mm_clk, db_reg_data_buf_mosi_arr(i), db_reg_data_buf_miso_arr(i));
PORT MAP(mm_rst, mm_clk, fn0_reg_diagnostics_mosi, fn0_reg_diagnostics_miso); u_mm_file_tm_tr_nonbo : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "FN") & "REG_TR_NONBONDED")
PORT MAP(mm_rst, mm_clk, mt_reg_tr_nonbonded_mosi_arr(i), mt_reg_tr_nonbonded_miso_arr(i));
u_mm_file_bn0_bg_ram_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG") u_mm_file_tm_reg_diag : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "FN") & "REG_DIAGNOSTICS_MESH")
PORT MAP(mm_rst, mm_clk, bn0_bg_ram_data_mosi, bn0_bg_ram_data_miso); PORT MAP(mm_rst, mm_clk, mt_reg_diagnostics_mosi_arr(i), mt_reg_diagnostics_miso_arr(i));
u_mm_file_bn0_bg_reg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG") END GENERATE;
PORT MAP(mm_rst, mm_clk, bn0_bg_reg_ctrl_mosi, bn0_bg_reg_ctrl_miso); -- Back nodes
u_mm_file_bn0_db_ram_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER") gen_mm_bn : FOR i IN c_nof_fn TO c_nof_nodes-1 GENERATE
PORT MAP(mm_rst, mm_clk, bn0_db_ram_data_buf_mosi, bn0_db_ram_data_buf_miso);
u_mm_file_bn0_db_reg_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER") u_mm_file_bg_ram_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "BN") & "RAM_DIAG_BG")
PORT MAP(mm_rst, mm_clk, bn0_db_reg_data_buf_mosi, bn0_db_reg_data_buf_miso); PORT MAP(mm_rst, mm_clk, bg_ram_data_mosi_arr(i), bg_ram_data_miso_arr(i));
u_mm_file_bn0_tm_tr_nonbo : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "REG_TR_NONBONDED") u_mm_file_bg_reg_diag : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "BN") & "REG_DIAG_BG")
PORT MAP(mm_rst, mm_clk, bn0_reg_tr_nonbonded_mosi, bn0_reg_tr_nonbonded_miso); PORT MAP(mm_rst, mm_clk, bg_reg_ctrl_mosi_arr(i), bg_reg_ctrl_miso_arr(i));
u_mm_file_bn0_tm_reg_diag : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAGNOSTICS_MESH") u_mm_file_db_ram_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "BN") & "RAM_DIAG_DATA_BUFFER")
PORT MAP(mm_rst, mm_clk, bn0_reg_diagnostics_mosi, bn0_reg_diagnostics_miso); PORT MAP(mm_rst, mm_clk, bg_ram_data_mosi_arr(i), bg_ram_data_miso_arr(i));
u_mm_file_db_reg_data : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "BN") & "REG_DIAG_DATA_BUFFER")
PORT MAP(mm_rst, mm_clk, db_reg_data_buf_mosi_arr(i), db_reg_data_buf_miso_arr(i));
u_mm_file_tm_tr_nonbo : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "BN") & "REG_TR_NONBONDED")
PORT MAP(mm_rst, mm_clk, mt_reg_tr_nonbonded_mosi_arr(i), mt_reg_tr_nonbonded_miso_arr(i));
u_mm_file_tm_reg_diag : mm_file GENERIC MAP(mmf_unb_file_prefix(0, i, "BN") & "REG_DIAGNOSTICS_MESH")
PORT MAP(mm_rst, mm_clk, mt_reg_diagnostics_mosi_arr(i), mt_reg_diagnostics_miso_arr(i));
END GENERATE;
END t_bench; END t_bench;
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