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Commit 840b7011 authored by Reinier van der Walle's avatar Reinier van der Walle
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cleanup

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1 merge request!331Resolve HPR-85
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libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd deleted 100644 → 0
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-------------------------------------------------------------------------------
--
-- Copyright 2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
-- Author: R. van der Walle
-- Purpose: Provide AXI4-Stream and AXI4-Lite interface for eth_tester.vhd such
-- that it can be used to create a Vivado IP block.
-- Description:
-- . The eth_tester_axi4_wrapper uses axi4_stream_dp_bridge to convert the dp
-- sosi/siso interfaces of the eth_tester into AXI4-Stream interfaces.
-- Similarly, axi4_lite_mm_bridge is used to convert the mem copi/cipo
-- interfaces into AXI4_Lite interfaces.
-- . In order for this component to be suitable as a Vivado IP, the ports are
-- exclusively STD_LOGIC(_VECTOR) where the widths are hard-coded as demanded
-- by the Vivado IP creator (only supports VHDL-93).
LIBRARY IEEE, common_lib, dp_lib, diag_lib, axi4_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.dp_components_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE axi4_lib.axi4_stream_pkg.ALL;
USE axi4_lib.axi4_lite_pkg.ALL;
USE work.eth_pkg.ALL;
USE work.eth_tester_pkg.ALL;
ENTITY eth_tester_axi4_wrapper IS
PORT (
-- Clocks and reset
mm_clk : IN STD_LOGIC;
st_clk : IN STD_LOGIC;
st_pps : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
-- UDP transmit interface
eth_src_mac : IN STD_LOGIC_VECTOR(6*8-1 DOWNTO 0);
ip_src_addr : IN STD_LOGIC_VECTOR(4*8-1 DOWNTO 0);
udp_src_port : IN STD_LOGIC_VECTOR(2*8-1 DOWNTO 0);
tx_fifo_rd_emp_arr : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-- tx_udp
-- Source In and Sink Out
tx_udp_tready : IN STD_LOGIC;
-- Source Out and Sink In
tx_udp_tvalid : OUT STD_LOGIC;
tx_udp_tdata : OUT STD_LOGIC_VECTOR(512-1 DOWNTO 0);
tx_udp_tstrb : OUT STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
tx_udp_tkeep : OUT STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
tx_udp_tlast : OUT STD_LOGIC;
tx_udp_tid : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
tx_udp_tdest : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
tx_udp_tuser : OUT STD_LOGIC_VECTOR(70-1 DOWNTO 0);
-- rx_udp
-- Source In and Sink Out
rx_udp_tready : OUT STD_LOGIC;
-- Source Out and Sink In
rx_udp_tvalid : IN STD_LOGIC;
rx_udp_tdata : IN STD_LOGIC_VECTOR(512-1 DOWNTO 0);
rx_udp_tstrb : IN STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
rx_udp_tkeep : IN STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
rx_udp_tlast : IN STD_LOGIC;
rx_udp_tid : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
rx_udp_tdest : IN STD_LOGIC_VECTOR(32-1 DOWNTO 0);
rx_udp_tuser : IN STD_LOGIC_VECTOR(70-1 DOWNTO 0);
-- reg_bg_ctrl
-- copi
reg_bg_ctrl_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bg_ctrl_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bg_ctrl_awvalid : IN STD_LOGIC;
reg_bg_ctrl_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bg_ctrl_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_bg_ctrl_wvalid : IN STD_LOGIC;
reg_bg_ctrl_bready : IN STD_LOGIC;
reg_bg_ctrl_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bg_ctrl_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bg_ctrl_arvalid : IN STD_LOGIC;
reg_bg_ctrl_rready : IN STD_LOGIC;
-- cipo
reg_bg_ctrl_awready : OUT STD_LOGIC;
reg_bg_ctrl_wready : OUT STD_LOGIC;
reg_bg_ctrl_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bg_ctrl_bvalid : OUT STD_LOGIC;
reg_bg_ctrl_arready : OUT STD_LOGIC;
reg_bg_ctrl_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_bg_ctrl_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bg_ctrl_rvalid : OUT STD_LOGIC;
-- reg_hdr_dat
-- copi
reg_hdr_dat_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_hdr_dat_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_hdr_dat_awvalid : IN STD_LOGIC;
reg_hdr_dat_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_hdr_dat_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_hdr_dat_wvalid : IN STD_LOGIC;
reg_hdr_dat_bready : IN STD_LOGIC;
reg_hdr_dat_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_hdr_dat_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_hdr_dat_arvalid : IN STD_LOGIC;
reg_hdr_dat_rready : IN STD_LOGIC;
-- cipo
reg_hdr_dat_awready : OUT STD_LOGIC;
reg_hdr_dat_wready : OUT STD_LOGIC;
reg_hdr_dat_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_hdr_dat_bvalid : OUT STD_LOGIC;
reg_hdr_dat_arready : OUT STD_LOGIC;
reg_hdr_dat_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_hdr_dat_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_hdr_dat_rvalid : OUT STD_LOGIC;
-- reg_bsn_monitor_v2_tx
-- copi
reg_bsn_monitor_v2_tx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_tx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bsn_monitor_v2_tx_awvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_tx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_tx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_bsn_monitor_v2_tx_wvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_tx_bready : IN STD_LOGIC;
reg_bsn_monitor_v2_tx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_tx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bsn_monitor_v2_tx_arvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_tx_rready : IN STD_LOGIC;
-- cipo
reg_bsn_monitor_v2_tx_awready : OUT STD_LOGIC;
reg_bsn_monitor_v2_tx_wready : OUT STD_LOGIC;
reg_bsn_monitor_v2_tx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bsn_monitor_v2_tx_bvalid : OUT STD_LOGIC;
reg_bsn_monitor_v2_tx_arready : OUT STD_LOGIC;
reg_bsn_monitor_v2_tx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_tx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bsn_monitor_v2_tx_rvalid : OUT STD_LOGIC;
-- reg_strobe_total_count_tx
-- copi
reg_strobe_total_count_tx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_tx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_strobe_total_count_tx_awvalid : IN STD_LOGIC;
reg_strobe_total_count_tx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_tx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_strobe_total_count_tx_wvalid : IN STD_LOGIC;
reg_strobe_total_count_tx_bready : IN STD_LOGIC;
reg_strobe_total_count_tx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_tx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_strobe_total_count_tx_arvalid : IN STD_LOGIC;
reg_strobe_total_count_tx_rready : IN STD_LOGIC;
-- cipo
reg_strobe_total_count_tx_awready : OUT STD_LOGIC;
reg_strobe_total_count_tx_wready : OUT STD_LOGIC;
reg_strobe_total_count_tx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_strobe_total_count_tx_bvalid : OUT STD_LOGIC;
reg_strobe_total_count_tx_arready : OUT STD_LOGIC;
reg_strobe_total_count_tx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_tx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_strobe_total_count_tx_rvalid : OUT STD_LOGIC;
-- reg_bsn_monitor_v2_rx
-- copi
reg_bsn_monitor_v2_rx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_rx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bsn_monitor_v2_rx_awvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_rx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_rx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_bsn_monitor_v2_rx_wvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_rx_bready : IN STD_LOGIC;
reg_bsn_monitor_v2_rx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_rx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bsn_monitor_v2_rx_arvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_rx_rready : IN STD_LOGIC;
-- cipo
reg_bsn_monitor_v2_rx_awready : OUT STD_LOGIC;
reg_bsn_monitor_v2_rx_wready : OUT STD_LOGIC;
reg_bsn_monitor_v2_rx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bsn_monitor_v2_rx_bvalid : OUT STD_LOGIC;
reg_bsn_monitor_v2_rx_arready : OUT STD_LOGIC;
reg_bsn_monitor_v2_rx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_rx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bsn_monitor_v2_rx_rvalid : OUT STD_LOGIC;
-- reg_strobe_total_count_rx
-- copi
reg_strobe_total_count_rx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_rx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_strobe_total_count_rx_awvalid : IN STD_LOGIC;
reg_strobe_total_count_rx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_rx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_strobe_total_count_rx_wvalid : IN STD_LOGIC;
reg_strobe_total_count_rx_bready : IN STD_LOGIC;
reg_strobe_total_count_rx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_rx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_strobe_total_count_rx_arvalid : IN STD_LOGIC;
reg_strobe_total_count_rx_rready : IN STD_LOGIC;
-- cipo
reg_strobe_total_count_rx_awready : OUT STD_LOGIC;
reg_strobe_total_count_rx_wready : OUT STD_LOGIC;
reg_strobe_total_count_rx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_strobe_total_count_rx_bvalid : OUT STD_LOGIC;
reg_strobe_total_count_rx_arready : OUT STD_LOGIC;
reg_strobe_total_count_rx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_rx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_strobe_total_count_rx_rvalid : OUT STD_LOGIC
);
END eth_tester_axi4_wrapper;
ARCHITECTURE str OF eth_tester_axi4_wrapper IS
SIGNAL rx_udp_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL rx_udp_siso_arr : t_dp_siso_arr(0 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL tx_udp_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL tx_udp_siso_arr : t_dp_siso_arr(0 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL rx_udp_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
SIGNAL rx_udp_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
SIGNAL tx_udp_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
SIGNAL tx_udp_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
SIGNAL reg_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_bg_ctrl_cipo : t_mem_cipo;
SIGNAL reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_hdr_dat_cipo : t_mem_cipo;
SIGNAL reg_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_bsn_monitor_v2_tx_cipo : t_mem_cipo;
SIGNAL reg_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_strobe_total_count_tx_cipo : t_mem_cipo;
SIGNAL reg_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_bsn_monitor_v2_rx_cipo : t_mem_cipo;
SIGNAL reg_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_strobe_total_count_rx_cipo : t_mem_cipo;
SIGNAL reg_bg_ctrl_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
SIGNAL reg_bg_ctrl_axi4_cipo : t_axi4_lite_cipo;
SIGNAL reg_hdr_dat_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
SIGNAL reg_hdr_dat_axi4_cipo : t_axi4_lite_cipo;
SIGNAL reg_bsn_monitor_v2_tx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
SIGNAL reg_bsn_monitor_v2_tx_axi4_cipo : t_axi4_lite_cipo;
SIGNAL reg_strobe_total_count_tx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
SIGNAL reg_strobe_total_count_tx_axi4_cipo : t_axi4_lite_cipo;
SIGNAL reg_bsn_monitor_v2_rx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
SIGNAL reg_bsn_monitor_v2_rx_axi4_cipo : t_axi4_lite_cipo;
SIGNAL reg_strobe_total_count_rx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
SIGNAL reg_strobe_total_count_rx_axi4_cipo : t_axi4_lite_cipo;
SIGNAL mm_rst : STD_LOGIC := '0';
SIGNAL st_rst : STD_LOGIC := '0';
BEGIN
u_eth_tester : ENTITY work.eth_tester
GENERIC MAP (
g_remove_crc => FALSE
)
PORT MAP (
-- Clocks and reset
mm_rst => mm_rst,
mm_clk => mm_clk,
st_rst => st_rst,
st_clk => st_clk,
st_pps => st_pps,
-- UDP transmit interface
eth_src_mac => eth_src_mac,
ip_src_addr => ip_src_addr,
udp_src_port => udp_src_port,
tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
tx_udp_sosi_arr => tx_udp_sosi_arr,
tx_udp_siso_arr => tx_udp_siso_arr,
-- UDP receive interface
rx_udp_sosi_arr => rx_udp_sosi_arr,
-- Memory Mapped Slaves (one per stream)
reg_bg_ctrl_copi => reg_bg_ctrl_copi,
reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
reg_hdr_dat_copi => reg_hdr_dat_copi,
reg_hdr_dat_cipo => reg_hdr_dat_cipo,
reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
);
-- DP to AXI4
u_axi4_tx_udp : ENTITY axi4_lib.axi4_stream_dp_bridge
GENERIC MAP (
g_axi4_rl => 0,
g_dp_rl => 1,
g_active_low_rst => TRUE
)
PORT MAP (
in_clk => st_clk,
in_rst => aresetn,
dp_rst => st_rst,
dp_in_sosi => tx_udp_sosi_arr(0),
dp_in_siso => tx_udp_siso_arr(0),
axi4_out_sosi => tx_udp_axi4_sosi,
axi4_out_siso => tx_udp_axi4_siso
);
u_axi4_rx_udp : ENTITY axi4_lib.axi4_stream_dp_bridge
GENERIC MAP (
g_axi4_rl => 0,
g_dp_rl => 1,
g_active_low_rst => TRUE
)
PORT MAP (
in_clk => st_clk,
in_rst => aresetn,
axi4_in_sosi => rx_udp_axi4_sosi,
axi4_in_siso => rx_udp_axi4_siso,
dp_out_sosi => rx_udp_sosi_arr(0),
dp_out_siso => rx_udp_siso_arr(0)
);
-- AXI4 to MM
u_axi4_reg_bg_ctrl : ENTITY axi4_lib.axi4_lite_mm_bridge
GENERIC MAP (
g_active_low_rst => TRUE
)
PORT MAP (
in_clk => mm_clk,
in_rst => aresetn,
mm_rst => mm_rst,
axi4_in_copi => reg_bg_ctrl_axi4_copi,
axi4_in_cipo => reg_bg_ctrl_axi4_cipo,
mm_out_copi => reg_bg_ctrl_copi,
mm_out_cipo => reg_bg_ctrl_cipo
);
u_axi4_reg_hdr_dat : ENTITY axi4_lib.axi4_lite_mm_bridge
GENERIC MAP (
g_active_low_rst => TRUE
)
PORT MAP (
in_clk => mm_clk,
in_rst => aresetn,
axi4_in_copi => reg_hdr_dat_axi4_copi,
axi4_in_cipo => reg_hdr_dat_axi4_cipo,
mm_out_copi => reg_hdr_dat_copi,
mm_out_cipo => reg_hdr_dat_cipo
);
u_axi4_reg_bsn_monitor_v2_tx : ENTITY axi4_lib.axi4_lite_mm_bridge
GENERIC MAP (
g_active_low_rst => TRUE
)
PORT MAP (
in_clk => mm_clk,
in_rst => aresetn,
axi4_in_copi => reg_bsn_monitor_v2_tx_axi4_copi,
axi4_in_cipo => reg_bsn_monitor_v2_tx_axi4_cipo,
mm_out_copi => reg_bsn_monitor_v2_tx_copi,
mm_out_cipo => reg_bsn_monitor_v2_tx_cipo
);
u_axi4_reg_strobe_total_count_tx : ENTITY axi4_lib.axi4_lite_mm_bridge
GENERIC MAP (
g_active_low_rst => TRUE
)
PORT MAP (
in_clk => mm_clk,
in_rst => aresetn,
axi4_in_copi => reg_strobe_total_count_tx_axi4_copi,
axi4_in_cipo => reg_strobe_total_count_tx_axi4_cipo,
mm_out_copi => reg_strobe_total_count_tx_copi,
mm_out_cipo => reg_strobe_total_count_tx_cipo
);
u_axi4_reg_bsn_monitor_v2_rx : ENTITY axi4_lib.axi4_lite_mm_bridge
GENERIC MAP (
g_active_low_rst => TRUE
)
PORT MAP (
in_clk => mm_clk,
in_rst => aresetn,
axi4_in_copi => reg_bsn_monitor_v2_rx_axi4_copi,
axi4_in_cipo => reg_bsn_monitor_v2_rx_axi4_cipo,
mm_out_copi => reg_bsn_monitor_v2_rx_copi,
mm_out_cipo => reg_bsn_monitor_v2_rx_cipo
);
u_axi4_reg_strobe_total_count_rx : ENTITY axi4_lib.axi4_lite_mm_bridge
GENERIC MAP (
g_active_low_rst => TRUE
)
PORT MAP (
in_clk => mm_clk,
in_rst => aresetn,
axi4_in_copi => reg_strobe_total_count_rx_axi4_copi,
axi4_in_cipo => reg_strobe_total_count_rx_axi4_cipo,
mm_out_copi => reg_strobe_total_count_rx_copi,
mm_out_cipo => reg_strobe_total_count_rx_cipo
);
-- Wire Records to IN/OUT ports.
-- tx_udp
tx_udp_axi4_siso.tready <= tx_udp_tready;
tx_udp_tvalid <= tx_udp_axi4_sosi.tvalid;
tx_udp_tdata <= tx_udp_axi4_sosi.tdata;
tx_udp_tstrb <= tx_udp_axi4_sosi.tstrb;
tx_udp_tkeep <= tx_udp_axi4_sosi.tkeep;
tx_udp_tlast <= tx_udp_axi4_sosi.tlast;
tx_udp_tid <= tx_udp_axi4_sosi.tid;
tx_udp_tdest <= tx_udp_axi4_sosi.tdest;
tx_udp_tuser <= tx_udp_axi4_sosi.tuser;
-- rx_udp
rx_udp_tready <= rx_udp_axi4_siso.tready;
rx_udp_axi4_sosi.tvalid <= rx_udp_tvalid;
rx_udp_axi4_sosi.tdata <= rx_udp_tdata;
rx_udp_axi4_sosi.tstrb <= rx_udp_tstrb;
rx_udp_axi4_sosi.tkeep <= rx_udp_tkeep;
rx_udp_axi4_sosi.tlast <= rx_udp_tlast;
rx_udp_axi4_sosi.tid <= rx_udp_tid;
rx_udp_axi4_sosi.tdest <= rx_udp_tdest;
rx_udp_axi4_sosi.tuser <= rx_udp_tuser;
-- reg_bg_ctrl
-- copi
reg_bg_ctrl_axi4_copi.awaddr <= reg_bg_ctrl_awaddr;
reg_bg_ctrl_axi4_copi.awprot <= reg_bg_ctrl_awprot;
reg_bg_ctrl_axi4_copi.awvalid <= reg_bg_ctrl_awvalid;
reg_bg_ctrl_axi4_copi.wdata <= reg_bg_ctrl_wdata;
reg_bg_ctrl_axi4_copi.wstrb <= reg_bg_ctrl_wstrb;
reg_bg_ctrl_axi4_copi.wvalid <= reg_bg_ctrl_wvalid;
reg_bg_ctrl_axi4_copi.bready <= reg_bg_ctrl_bready;
reg_bg_ctrl_axi4_copi.araddr <= reg_bg_ctrl_araddr;
reg_bg_ctrl_axi4_copi.arprot <= reg_bg_ctrl_arprot;
reg_bg_ctrl_axi4_copi.arvalid <= reg_bg_ctrl_arvalid;
reg_bg_ctrl_axi4_copi.rready <= reg_bg_ctrl_rready;
-- cipo
reg_bg_ctrl_awready <= reg_bg_ctrl_axi4_cipo.awready;
reg_bg_ctrl_wready <= reg_bg_ctrl_axi4_cipo.wready;
reg_bg_ctrl_bresp <= reg_bg_ctrl_axi4_cipo.bresp;
reg_bg_ctrl_bvalid <= reg_bg_ctrl_axi4_cipo.bvalid;
reg_bg_ctrl_arready <= reg_bg_ctrl_axi4_cipo.arready;
reg_bg_ctrl_rdata <= reg_bg_ctrl_axi4_cipo.rdata;
reg_bg_ctrl_rresp <= reg_bg_ctrl_axi4_cipo.rresp;
reg_bg_ctrl_rvalid <= reg_bg_ctrl_axi4_cipo.rvalid;
-- reg_hdr_dat
-- copi
reg_hdr_dat_axi4_copi.awaddr <= reg_hdr_dat_awaddr;
reg_hdr_dat_axi4_copi.awprot <= reg_hdr_dat_awprot;
reg_hdr_dat_axi4_copi.awvalid <= reg_hdr_dat_awvalid;
reg_hdr_dat_axi4_copi.wdata <= reg_hdr_dat_wdata;
reg_hdr_dat_axi4_copi.wstrb <= reg_hdr_dat_wstrb;
reg_hdr_dat_axi4_copi.wvalid <= reg_hdr_dat_wvalid;
reg_hdr_dat_axi4_copi.bready <= reg_hdr_dat_bready;
reg_hdr_dat_axi4_copi.araddr <= reg_hdr_dat_araddr;
reg_hdr_dat_axi4_copi.arprot <= reg_hdr_dat_arprot;
reg_hdr_dat_axi4_copi.arvalid <= reg_hdr_dat_arvalid;
reg_hdr_dat_axi4_copi.rready <= reg_hdr_dat_rready;
-- cipo
reg_hdr_dat_awready <= reg_hdr_dat_axi4_cipo.awready;
reg_hdr_dat_wready <= reg_hdr_dat_axi4_cipo.wready;
reg_hdr_dat_bresp <= reg_hdr_dat_axi4_cipo.bresp;
reg_hdr_dat_bvalid <= reg_hdr_dat_axi4_cipo.bvalid;
reg_hdr_dat_arready <= reg_hdr_dat_axi4_cipo.arready;
reg_hdr_dat_rdata <= reg_hdr_dat_axi4_cipo.rdata;
reg_hdr_dat_rresp <= reg_hdr_dat_axi4_cipo.rresp;
reg_hdr_dat_rvalid <= reg_hdr_dat_axi4_cipo.rvalid;
-- reg_bsn_monitor_v2_tx
-- copi
reg_bsn_monitor_v2_tx_axi4_copi.awaddr <= reg_bsn_monitor_v2_tx_awaddr;
reg_bsn_monitor_v2_tx_axi4_copi.awprot <= reg_bsn_monitor_v2_tx_awprot;
reg_bsn_monitor_v2_tx_axi4_copi.awvalid <= reg_bsn_monitor_v2_tx_awvalid;
reg_bsn_monitor_v2_tx_axi4_copi.wdata <= reg_bsn_monitor_v2_tx_wdata;
reg_bsn_monitor_v2_tx_axi4_copi.wstrb <= reg_bsn_monitor_v2_tx_wstrb;
reg_bsn_monitor_v2_tx_axi4_copi.wvalid <= reg_bsn_monitor_v2_tx_wvalid;
reg_bsn_monitor_v2_tx_axi4_copi.bready <= reg_bsn_monitor_v2_tx_bready;
reg_bsn_monitor_v2_tx_axi4_copi.araddr <= reg_bsn_monitor_v2_tx_araddr;
reg_bsn_monitor_v2_tx_axi4_copi.arprot <= reg_bsn_monitor_v2_tx_arprot;
reg_bsn_monitor_v2_tx_axi4_copi.arvalid <= reg_bsn_monitor_v2_tx_arvalid;
reg_bsn_monitor_v2_tx_axi4_copi.rready <= reg_bsn_monitor_v2_tx_rready;
-- cipo
reg_bsn_monitor_v2_tx_awready <= reg_bsn_monitor_v2_tx_axi4_cipo.awready;
reg_bsn_monitor_v2_tx_wready <= reg_bsn_monitor_v2_tx_axi4_cipo.wready;
reg_bsn_monitor_v2_tx_bresp <= reg_bsn_monitor_v2_tx_axi4_cipo.bresp;
reg_bsn_monitor_v2_tx_bvalid <= reg_bsn_monitor_v2_tx_axi4_cipo.bvalid;
reg_bsn_monitor_v2_tx_arready <= reg_bsn_monitor_v2_tx_axi4_cipo.arready;
reg_bsn_monitor_v2_tx_rdata <= reg_bsn_monitor_v2_tx_axi4_cipo.rdata;
reg_bsn_monitor_v2_tx_rresp <= reg_bsn_monitor_v2_tx_axi4_cipo.rresp;
reg_bsn_monitor_v2_tx_rvalid <= reg_bsn_monitor_v2_tx_axi4_cipo.rvalid;
-- reg_strobe_total_count_tx
-- copi
reg_strobe_total_count_tx_axi4_copi.awaddr <= reg_strobe_total_count_tx_awaddr;
reg_strobe_total_count_tx_axi4_copi.awprot <= reg_strobe_total_count_tx_awprot;
reg_strobe_total_count_tx_axi4_copi.awvalid <= reg_strobe_total_count_tx_awvalid;
reg_strobe_total_count_tx_axi4_copi.wdata <= reg_strobe_total_count_tx_wdata;
reg_strobe_total_count_tx_axi4_copi.wstrb <= reg_strobe_total_count_tx_wstrb;
reg_strobe_total_count_tx_axi4_copi.wvalid <= reg_strobe_total_count_tx_wvalid;
reg_strobe_total_count_tx_axi4_copi.bready <= reg_strobe_total_count_tx_bready;
reg_strobe_total_count_tx_axi4_copi.araddr <= reg_strobe_total_count_tx_araddr;
reg_strobe_total_count_tx_axi4_copi.arprot <= reg_strobe_total_count_tx_arprot;
reg_strobe_total_count_tx_axi4_copi.arvalid <= reg_strobe_total_count_tx_arvalid;
reg_strobe_total_count_tx_axi4_copi.rready <= reg_strobe_total_count_tx_rready;
-- cipo
reg_strobe_total_count_tx_awready <= reg_strobe_total_count_tx_axi4_cipo.awready;
reg_strobe_total_count_tx_wready <= reg_strobe_total_count_tx_axi4_cipo.wready;
reg_strobe_total_count_tx_bresp <= reg_strobe_total_count_tx_axi4_cipo.bresp;
reg_strobe_total_count_tx_bvalid <= reg_strobe_total_count_tx_axi4_cipo.bvalid;
reg_strobe_total_count_tx_arready <= reg_strobe_total_count_tx_axi4_cipo.arready;
reg_strobe_total_count_tx_rdata <= reg_strobe_total_count_tx_axi4_cipo.rdata;
reg_strobe_total_count_tx_rresp <= reg_strobe_total_count_tx_axi4_cipo.rresp;
reg_strobe_total_count_tx_rvalid <= reg_strobe_total_count_tx_axi4_cipo.rvalid;
-- reg_bsn_monitor_v2_rx
-- copi
reg_bsn_monitor_v2_rx_axi4_copi.awaddr <= reg_bsn_monitor_v2_rx_awaddr;
reg_bsn_monitor_v2_rx_axi4_copi.awprot <= reg_bsn_monitor_v2_rx_awprot;
reg_bsn_monitor_v2_rx_axi4_copi.awvalid <= reg_bsn_monitor_v2_rx_awvalid;
reg_bsn_monitor_v2_rx_axi4_copi.wdata <= reg_bsn_monitor_v2_rx_wdata;
reg_bsn_monitor_v2_rx_axi4_copi.wstrb <= reg_bsn_monitor_v2_rx_wstrb;
reg_bsn_monitor_v2_rx_axi4_copi.wvalid <= reg_bsn_monitor_v2_rx_wvalid;
reg_bsn_monitor_v2_rx_axi4_copi.bready <= reg_bsn_monitor_v2_rx_bready;
reg_bsn_monitor_v2_rx_axi4_copi.araddr <= reg_bsn_monitor_v2_rx_araddr;
reg_bsn_monitor_v2_rx_axi4_copi.arprot <= reg_bsn_monitor_v2_rx_arprot;
reg_bsn_monitor_v2_rx_axi4_copi.arvalid <= reg_bsn_monitor_v2_rx_arvalid;
reg_bsn_monitor_v2_rx_axi4_copi.rready <= reg_bsn_monitor_v2_rx_rready;
-- cipo
reg_bsn_monitor_v2_rx_awready <= reg_bsn_monitor_v2_rx_axi4_cipo.awready;
reg_bsn_monitor_v2_rx_wready <= reg_bsn_monitor_v2_rx_axi4_cipo.wready;
reg_bsn_monitor_v2_rx_bresp <= reg_bsn_monitor_v2_rx_axi4_cipo.bresp;
reg_bsn_monitor_v2_rx_bvalid <= reg_bsn_monitor_v2_rx_axi4_cipo.bvalid;
reg_bsn_monitor_v2_rx_arready <= reg_bsn_monitor_v2_rx_axi4_cipo.arready;
reg_bsn_monitor_v2_rx_rdata <= reg_bsn_monitor_v2_rx_axi4_cipo.rdata;
reg_bsn_monitor_v2_rx_rresp <= reg_bsn_monitor_v2_rx_axi4_cipo.rresp;
reg_bsn_monitor_v2_rx_rvalid <= reg_bsn_monitor_v2_rx_axi4_cipo.rvalid;
-- reg_strobe_total_count_rx
-- copi
reg_strobe_total_count_rx_axi4_copi.awaddr <= reg_strobe_total_count_rx_awaddr;
reg_strobe_total_count_rx_axi4_copi.awprot <= reg_strobe_total_count_rx_awprot;
reg_strobe_total_count_rx_axi4_copi.awvalid <= reg_strobe_total_count_rx_awvalid;
reg_strobe_total_count_rx_axi4_copi.wdata <= reg_strobe_total_count_rx_wdata;
reg_strobe_total_count_rx_axi4_copi.wstrb <= reg_strobe_total_count_rx_wstrb;
reg_strobe_total_count_rx_axi4_copi.wvalid <= reg_strobe_total_count_rx_wvalid;
reg_strobe_total_count_rx_axi4_copi.bready <= reg_strobe_total_count_rx_bready;
reg_strobe_total_count_rx_axi4_copi.araddr <= reg_strobe_total_count_rx_araddr;
reg_strobe_total_count_rx_axi4_copi.arprot <= reg_strobe_total_count_rx_arprot;
reg_strobe_total_count_rx_axi4_copi.arvalid <= reg_strobe_total_count_rx_arvalid;
reg_strobe_total_count_rx_axi4_copi.rready <= reg_strobe_total_count_rx_rready;
-- cipo
reg_strobe_total_count_rx_awready <= reg_strobe_total_count_rx_axi4_cipo.awready;
reg_strobe_total_count_rx_wready <= reg_strobe_total_count_rx_axi4_cipo.wready;
reg_strobe_total_count_rx_bresp <= reg_strobe_total_count_rx_axi4_cipo.bresp;
reg_strobe_total_count_rx_bvalid <= reg_strobe_total_count_rx_axi4_cipo.bvalid;
reg_strobe_total_count_rx_arready <= reg_strobe_total_count_rx_axi4_cipo.arready;
reg_strobe_total_count_rx_rdata <= reg_strobe_total_count_rx_axi4_cipo.rdata;
reg_strobe_total_count_rx_rresp <= reg_strobe_total_count_rx_axi4_cipo.rresp;
reg_strobe_total_count_rx_rvalid <= reg_strobe_total_count_rx_axi4_cipo.rvalid;
END str;
libraries/io/eth/src/vhdl/eth_tester_vivado_ip_wrapper.vhd
+ 33
− 34
View file @ 840b7011
...@@ -18,14 +18,15 @@ ...@@ -18,14 +18,15 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Author: R. van der Walle -- Author: R. van der Walle
-- Purpose: Provide AXI-4-stream interfaces for eth_tester.vhd such -- Purpose: Provide AXI-4-stream interfaces + standard avalon MM interfaces for
-- that it can be used to create a Vivado IP block. -- eth_tester.vhd such that it can be used to create a Vivado IP block.
-- Description: -- Description:
-- . The eth_tester_vivado_ip_wrapper uses axi4_stream_dp_bridge to convert the dp -- . The eth_tester_vivado_ip_wrapper uses axi4_stream_dp_bridge to convert the dp
-- sosi/siso interfaces of the eth_tester into AXI4-Stream interfaces. -- sosi/siso interfaces of the eth_tester into AXI4-Stream interfaces.
-- . In order for this component to be suitable as a Vivado IP, the ports are -- . In order for this component to be suitable as a Vivado IP, the ports are
-- exclusively STD_LOGIC(_VECTOR) where the widths are hard-coded as demanded -- exclusively STD_LOGIC(_VECTOR) where the widths are hard-coded as demanded
-- by the Vivado IP creator (only supports VHDL-93). -- by the Vivado IP creator (only supports VHDL-93).
-- Remark
-- . Avalon is used for all MM interfaces, which can be bridged to AXI4-Lite in -- . Avalon is used for all MM interfaces, which can be bridged to AXI4-Lite in
-- vivado using the AXI AMM Bridge IP. -- vivado using the AXI AMM Bridge IP.
...@@ -166,7 +167,6 @@ ARCHITECTURE str OF eth_tester_vivado_ip_wrapper IS ...@@ -166,7 +167,6 @@ ARCHITECTURE str OF eth_tester_vivado_ip_wrapper IS
SIGNAL reg_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst; SIGNAL reg_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_strobe_total_count_rx_cipo : t_mem_cipo; SIGNAL reg_strobe_total_count_rx_cipo : t_mem_cipo;
SIGNAL mm_rst : STD_LOGIC := '0'; SIGNAL mm_rst : STD_LOGIC := '0';
SIGNAL st_rst : STD_LOGIC := '0'; SIGNAL st_rst : STD_LOGIC := '0';
...@@ -252,7 +252,6 @@ BEGIN ...@@ -252,7 +252,6 @@ BEGIN
-- Wire Records to IN/OUT ports. -- Wire Records to IN/OUT ports.
-- tx_udp -- tx_udp
tx_udp_axi4_siso.tready <= tx_udp_tready; tx_udp_axi4_siso.tready <= tx_udp_tready;
...@@ -280,66 +279,66 @@ BEGIN ...@@ -280,66 +279,66 @@ BEGIN
-- reg_bg_ctrl -- reg_bg_ctrl
-- copi -- copi
reg_bg_ctrl_copi.address <= reg_bg_ctrl_avm_address; reg_bg_ctrl_copi.address <= reg_bg_ctrl_avm_address;
reg_bg_ctrl_copi.wrdata(31 downto 0) <= reg_bg_ctrl_avm_writedata; reg_bg_ctrl_copi.wrdata <= RESIZE_UVEC(reg_bg_ctrl_avm_writedata, c_mem_data_w);
reg_bg_ctrl_copi.wr <= reg_bg_ctrl_avm_write; reg_bg_ctrl_copi.wr <= reg_bg_ctrl_avm_write;
reg_bg_ctrl_copi.rd <= reg_bg_ctrl_avm_read; reg_bg_ctrl_copi.rd <= reg_bg_ctrl_avm_read;
-- cipo -- cipo
reg_bg_ctrl_avm_readdata <= reg_bg_ctrl_cipo.rddata(31 downto 0); reg_bg_ctrl_avm_readdata <= RESIZE_UVEC_32(reg_bg_ctrl_cipo.rddata);
reg_bg_ctrl_avm_readdatavalid <= reg_bg_ctrl_cipo.rdval; reg_bg_ctrl_avm_readdatavalid <= reg_bg_ctrl_cipo.rdval;
reg_bg_ctrl_avm_waitrequest <= reg_bg_ctrl_cipo.waitrequest; reg_bg_ctrl_avm_waitrequest <= reg_bg_ctrl_cipo.waitrequest;
-- reg_hdr_dat -- reg_hdr_dat
-- copi -- copi
reg_hdr_dat_copi.address <= reg_hdr_dat_avm_address; reg_hdr_dat_copi.address <= reg_hdr_dat_avm_address;
reg_hdr_dat_copi.wrdata(31 downto 0) <= reg_hdr_dat_avm_writedata; reg_hdr_dat_copi.wrdata <= RESIZE_UVEC(reg_hdr_dat_avm_writedata, c_mem_data_w);
reg_hdr_dat_copi.wr <= reg_hdr_dat_avm_write; reg_hdr_dat_copi.wr <= reg_hdr_dat_avm_write;
reg_hdr_dat_copi.rd <= reg_hdr_dat_avm_read; reg_hdr_dat_copi.rd <= reg_hdr_dat_avm_read;
-- cipo -- cipo
reg_hdr_dat_avm_readdata <= reg_hdr_dat_cipo.rddata(31 downto 0); reg_hdr_dat_avm_readdata <= RESIZE_UVEC_32(reg_hdr_dat_cipo.rddata);
reg_hdr_dat_avm_readdatavalid <= reg_hdr_dat_cipo.rdval; reg_hdr_dat_avm_readdatavalid <= reg_hdr_dat_cipo.rdval;
reg_hdr_dat_avm_waitrequest <= reg_hdr_dat_cipo.waitrequest; reg_hdr_dat_avm_waitrequest <= reg_hdr_dat_cipo.waitrequest;
-- reg_bsn_monitor_v2_tx -- reg_bsn_monitor_v2_tx
-- copi -- copi
reg_bsn_monitor_v2_tx_copi.address <= reg_bsn_monitor_v2_tx_avm_address; reg_bsn_monitor_v2_tx_copi.address <= reg_bsn_monitor_v2_tx_avm_address;
reg_bsn_monitor_v2_tx_copi.wrdata(31 downto 0) <= reg_bsn_monitor_v2_tx_avm_writedata; reg_bsn_monitor_v2_tx_copi.wrdata <= RESIZE_UVEC(reg_bsn_monitor_v2_tx_avm_writedata, c_mem_data_w);
reg_bsn_monitor_v2_tx_copi.wr <= reg_bsn_monitor_v2_tx_avm_write; reg_bsn_monitor_v2_tx_copi.wr <= reg_bsn_monitor_v2_tx_avm_write;
reg_bsn_monitor_v2_tx_copi.rd <= reg_bsn_monitor_v2_tx_avm_read; reg_bsn_monitor_v2_tx_copi.rd <= reg_bsn_monitor_v2_tx_avm_read;
-- cipo -- cipo
reg_bsn_monitor_v2_tx_avm_readdata <= reg_bsn_monitor_v2_tx_cipo.rddata(31 downto 0); reg_bsn_monitor_v2_tx_avm_readdata <= RESIZE_UVEC_32(reg_bsn_monitor_v2_tx_cipo.rddata);
reg_bsn_monitor_v2_tx_avm_readdatavalid <= reg_bsn_monitor_v2_tx_cipo.rdval; reg_bsn_monitor_v2_tx_avm_readdatavalid <= reg_bsn_monitor_v2_tx_cipo.rdval;
reg_bsn_monitor_v2_tx_avm_waitrequest <= reg_bsn_monitor_v2_tx_cipo.waitrequest; reg_bsn_monitor_v2_tx_avm_waitrequest <= reg_bsn_monitor_v2_tx_cipo.waitrequest;
-- reg_strobe_total_count_tx -- reg_strobe_total_count_tx
-- copi -- copi
reg_strobe_total_count_tx_copi.address <= reg_strobe_total_count_tx_avm_address; reg_strobe_total_count_tx_copi.address <= reg_strobe_total_count_tx_avm_address;
reg_strobe_total_count_tx_copi.wrdata(31 downto 0) <= reg_strobe_total_count_tx_avm_writedata; reg_strobe_total_count_tx_copi.wrdata <= RESIZE_UVEC(reg_strobe_total_count_tx_avm_writedata, c_mem_data_w);
reg_strobe_total_count_tx_copi.wr <= reg_strobe_total_count_tx_avm_write; reg_strobe_total_count_tx_copi.wr <= reg_strobe_total_count_tx_avm_write;
reg_strobe_total_count_tx_copi.rd <= reg_strobe_total_count_tx_avm_read; reg_strobe_total_count_tx_copi.rd <= reg_strobe_total_count_tx_avm_read;
-- cipo -- cipo
reg_strobe_total_count_tx_avm_readdata <= reg_strobe_total_count_tx_cipo.rddata(31 downto 0); reg_strobe_total_count_tx_avm_readdata <= RESIZE_UVEC_32(reg_strobe_total_count_tx_cipo.rddata);
reg_strobe_total_count_tx_avm_readdatavalid <= reg_strobe_total_count_tx_cipo.rdval; reg_strobe_total_count_tx_avm_readdatavalid <= reg_strobe_total_count_tx_cipo.rdval;
reg_strobe_total_count_tx_avm_waitrequest <= reg_strobe_total_count_tx_cipo.waitrequest; reg_strobe_total_count_tx_avm_waitrequest <= reg_strobe_total_count_tx_cipo.waitrequest;
-- reg_bsn_monitor_v2_rx -- reg_bsn_monitor_v2_rx
-- copi -- copi
reg_bsn_monitor_v2_rx_copi.address <= reg_bsn_monitor_v2_rx_avm_address; reg_bsn_monitor_v2_rx_copi.address <= reg_bsn_monitor_v2_rx_avm_address;
reg_bsn_monitor_v2_rx_copi.wrdata(31 downto 0) <= reg_bsn_monitor_v2_rx_avm_writedata; reg_bsn_monitor_v2_rx_copi.wrdata <= RESIZE_UVEC(reg_bsn_monitor_v2_rx_avm_writedata, c_mem_data_w);
reg_bsn_monitor_v2_rx_copi.wr <= reg_bsn_monitor_v2_rx_avm_write; reg_bsn_monitor_v2_rx_copi.wr <= reg_bsn_monitor_v2_rx_avm_write;
reg_bsn_monitor_v2_rx_copi.rd <= reg_bsn_monitor_v2_rx_avm_read; reg_bsn_monitor_v2_rx_copi.rd <= reg_bsn_monitor_v2_rx_avm_read;
-- cipo -- cipo
reg_bsn_monitor_v2_rx_avm_readdata <= reg_bsn_monitor_v2_rx_cipo.rddata(31 downto 0); reg_bsn_monitor_v2_rx_avm_readdata <= RESIZE_UVEC_32(reg_bsn_monitor_v2_rx_cipo.rddata);
reg_bsn_monitor_v2_rx_avm_readdatavalid <= reg_bsn_monitor_v2_rx_cipo.rdval; reg_bsn_monitor_v2_rx_avm_readdatavalid <= reg_bsn_monitor_v2_rx_cipo.rdval;
reg_bsn_monitor_v2_rx_avm_waitrequest <= reg_bsn_monitor_v2_rx_cipo.waitrequest; reg_bsn_monitor_v2_rx_avm_waitrequest <= reg_bsn_monitor_v2_rx_cipo.waitrequest;
-- reg_strobe_total_count_rx -- reg_strobe_total_count_rx
-- copi -- copi
reg_strobe_total_count_rx_copi.address <= reg_strobe_total_count_rx_avm_address; reg_strobe_total_count_rx_copi.address <= reg_strobe_total_count_rx_avm_address;
reg_strobe_total_count_rx_copi.wrdata(31 downto 0) <= reg_strobe_total_count_rx_avm_writedata; reg_strobe_total_count_rx_copi.wrdata <= RESIZE_UVEC(reg_strobe_total_count_rx_avm_writedata, c_mem_data_w);
reg_strobe_total_count_rx_copi.wr <= reg_strobe_total_count_rx_avm_write; reg_strobe_total_count_rx_copi.wr <= reg_strobe_total_count_rx_avm_write;
reg_strobe_total_count_rx_copi.rd <= reg_strobe_total_count_rx_avm_read; reg_strobe_total_count_rx_copi.rd <= reg_strobe_total_count_rx_avm_read;
-- cipo -- cipo
reg_strobe_total_count_rx_avm_readdata <= reg_strobe_total_count_rx_cipo.rddata(31 downto 0); reg_strobe_total_count_rx_avm_readdata <= RESIZE_UVEC_32(reg_strobe_total_count_rx_cipo.rddata);
reg_strobe_total_count_rx_avm_readdatavalid <= reg_strobe_total_count_rx_cipo.rdval; reg_strobe_total_count_rx_avm_readdatavalid <= reg_strobe_total_count_rx_cipo.rdval;
reg_strobe_total_count_rx_avm_waitrequest <= reg_strobe_total_count_rx_cipo.waitrequest; reg_strobe_total_count_rx_avm_waitrequest <= reg_strobe_total_count_rx_cipo.waitrequest;
......
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