Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container Registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
83d35877
Commit
83d35877
authored
5 years ago
by
Eric Kooistra
Browse files
Options
Downloads
Patches
Plain Diff
Added array_and() and array_or() functions for t_nat_boolean_arr.
parent
c199ec2b
No related branches found
Branches containing commit
No related tags found
2 merge requests
!28
Master
,
!15
Resolve L2SDP-27
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
libraries/base/common/src/vhdl/common_pkg.vhd
+17
-0
17 additions, 0 deletions
libraries/base/common/src/vhdl/common_pkg.vhd
with
17 additions
and
0 deletions
libraries/base/common/src/vhdl/common_pkg.vhd
+
17
−
0
View file @
83d35877
...
@@ -206,6 +206,9 @@ PACKAGE common_pkg IS
...
@@ -206,6 +206,9 @@ PACKAGE common_pkg IS
FUNCTION
orv
(
slv
:
STD_LOGIC_VECTOR
)
RETURN
STD_LOGIC
;
-- alias of vector_or
FUNCTION
orv
(
slv
:
STD_LOGIC_VECTOR
)
RETURN
STD_LOGIC
;
-- alias of vector_or
FUNCTION
xorv
(
slv
:
STD_LOGIC_VECTOR
)
RETURN
STD_LOGIC
;
-- alias of vector_xor
FUNCTION
xorv
(
slv
:
STD_LOGIC_VECTOR
)
RETURN
STD_LOGIC
;
-- alias of vector_xor
FUNCTION
array_and
(
arr
:
t_nat_boolean_arr
)
RETURN
BOOLEAN
;
FUNCTION
array_or
(
arr
:
t_nat_boolean_arr
)
RETURN
BOOLEAN
;
FUNCTION
matrix_and
(
mat
:
t_sl_matrix
;
wi
,
wj
:
NATURAL
)
RETURN
STD_LOGIC
;
-- '1' when all matrix bits are '1' else '0'
FUNCTION
matrix_and
(
mat
:
t_sl_matrix
;
wi
,
wj
:
NATURAL
)
RETURN
STD_LOGIC
;
-- '1' when all matrix bits are '1' else '0'
FUNCTION
matrix_or
(
mat
:
t_sl_matrix
;
wi
,
wj
:
NATURAL
)
RETURN
STD_LOGIC
;
-- '0' when all matrix bits are '0' else '1'
FUNCTION
matrix_or
(
mat
:
t_sl_matrix
;
wi
,
wj
:
NATURAL
)
RETURN
STD_LOGIC
;
-- '0' when all matrix bits are '0' else '1'
...
@@ -757,6 +760,20 @@ PACKAGE BODY common_pkg IS
...
@@ -757,6 +760,20 @@ PACKAGE BODY common_pkg IS
RETURN
vector_tree
(
slv
,
"XOR"
);
RETURN
vector_tree
(
slv
,
"XOR"
);
END
;
END
;
FUNCTION
array_and
(
arr
:
t_nat_boolean_arr
)
RETURN
BOOLEAN
IS
VARIABLE
v_slv
:
STD_LOGIC_VECTOR
(
arr
'RANGE
);
BEGIN
FOR
I
IN
arr
'RANGE
LOOP
v_slv
(
I
)
:
=
sel_a_b
(
arr
(
I
),
'1'
,
'0'
);
END
LOOP
;
-- wire map boolean arr to slv
RETURN
sel_a_b
(
vector_and
(
v_slv
)
=
'1'
,
TRUE
,
FALSE
);
-- use vector_tree to determine result
END
;
FUNCTION
array_or
(
arr
:
t_nat_boolean_arr
)
RETURN
BOOLEAN
IS
VARIABLE
v_slv
:
STD_LOGIC_VECTOR
(
arr
'RANGE
);
BEGIN
FOR
I
IN
arr
'RANGE
LOOP
v_slv
(
I
)
:
=
sel_a_b
(
arr
(
I
),
'1'
,
'0'
);
END
LOOP
;
-- wire map boolean arr to slv
RETURN
sel_a_b
(
vector_or
(
v_slv
)
=
'1'
,
TRUE
,
FALSE
);
-- use vector_tree to determine result
END
;
FUNCTION
matrix_and
(
mat
:
t_sl_matrix
;
wi
,
wj
:
NATURAL
)
RETURN
STD_LOGIC
IS
FUNCTION
matrix_and
(
mat
:
t_sl_matrix
;
wi
,
wj
:
NATURAL
)
RETURN
STD_LOGIC
IS
VARIABLE
v_mat
:
t_sl_matrix
(
0
TO
wi
-1
,
0
TO
wj
-1
)
:
=
mat
;
-- map to fixed range
VARIABLE
v_mat
:
t_sl_matrix
(
0
TO
wi
-1
,
0
TO
wj
-1
)
:
=
mat
;
-- map to fixed range
VARIABLE
v_result
:
STD_LOGIC
:
=
'1'
;
VARIABLE
v_result
:
STD_LOGIC
:
=
'1'
;
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment