cosmetic

boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd

@@ -589,6 +589,13 @@ BEGIN
   
     
 
+
+
+  ------------------------------------------------------------------------------
+  -- Ethernet 1GbE
+  ------------------------------------------------------------------------------
+
+  -- Separate clkbuf for the 1GbE tse_clk:
   u_tse_clk_buf : ENTITY tech_clkbuf_lib.tech_clkbuf
   GENERIC MAP (
     g_technology   => g_technology,
@@ -598,70 +605,66 @@ BEGIN
     inclk  => i_xo_ethclk,
     outclk => i_tse_clk
   );
-
-
-  ------------------------------------------------------------------------------
-  -- Ethernet 1GbE
-  ------------------------------------------------------------------------------
   
-    gen_same_clk: IF g_udp_offload=TRUE GENERATE
 
-      eth1g_st_clk <= dp_clk_in;
-      eth1g_st_rst <= dp_rst_in;
+  gen_same_clk: IF g_udp_offload=TRUE GENERATE
 
-      gen_offload_io: FOR i IN 0 TO g_udp_offload_nof_streams-1 GENERATE
-        eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
-        udp_tx_siso_arr(i)       <= eth1g_udp_tx_siso_arr(i);
-  
-        udp_rx_sosi_arr(i)       <= eth1g_udp_rx_sosi_arr(i);
-        eth1g_udp_rx_siso_arr(i) <= udp_rx_siso_arr(i);
-      END GENERATE;
+    eth1g_st_clk <= dp_clk_in;
+    eth1g_st_rst <= dp_rst_in;
 
+    gen_offload_io: FOR i IN 0 TO g_udp_offload_nof_streams-1 GENERATE
+      eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
+      udp_tx_siso_arr(i)       <= eth1g_udp_tx_siso_arr(i);
+  
+      udp_rx_sosi_arr(i)       <= eth1g_udp_rx_sosi_arr(i);
+      eth1g_udp_rx_siso_arr(i) <= udp_rx_siso_arr(i);
     END GENERATE;
 
-    gen_separate_clk: IF g_udp_offload=FALSE GENERATE
-      eth1g_st_clk <= i_mm_clk;
-      eth1g_st_rst <= eth1g_mm_rst;
-    END GENERATE;
+  END GENERATE;
 
+  gen_separate_clk: IF g_udp_offload=FALSE GENERATE
+    eth1g_st_clk <= i_mm_clk;
+    eth1g_st_rst <= eth1g_mm_rst;
+  END GENERATE;
 
-    gen_mac: IF g_sim = FALSE GENERATE
-      u_mac : ENTITY eth_lib.eth
-      GENERIC MAP (
-        g_technology         => g_technology,
-        g_cross_clock_domain => g_udp_offload
-      )
-      PORT MAP (
-        -- Clocks and reset
-        mm_rst            => eth1g_mm_rst, -- use reset from QSYS
-        mm_clk            => i_mm_clk,     -- use mm_clk direct
-        eth_clk           => i_tse_clk,    -- 125 MHz clock
-        st_rst            => eth1g_st_rst,
-        st_clk            => eth1g_st_clk,       
-      
-        -- UDP transmit interface
-        udp_tx_snk_in_arr  => eth1g_udp_tx_sosi_arr, 
-        udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
-        -- UDP receive interface
-        udp_rx_src_in_arr  => eth1g_udp_rx_siso_arr,
-        udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+  gen_mac: IF g_sim = FALSE GENERATE
+    u_mac : ENTITY eth_lib.eth
+    GENERIC MAP (
+      g_technology         => g_technology,
+      g_cross_clock_domain => g_udp_offload
+    )
+    PORT MAP (
+      -- Clocks and reset
+      mm_rst            => eth1g_mm_rst, -- use reset from QSYS
+      mm_clk            => i_mm_clk,     -- use mm_clk direct
+      eth_clk           => i_tse_clk,    -- 125 MHz clock
+      st_rst            => eth1g_st_rst,
+      st_clk            => eth1g_st_clk,       
+    
+      -- UDP transmit interface
+      udp_tx_snk_in_arr  => eth1g_udp_tx_sosi_arr, 
+      udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+      -- UDP receive interface
+      udp_rx_src_in_arr  => eth1g_udp_rx_siso_arr,
+      udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
  
-        -- Memory Mapped Slaves
-        tse_sla_in        => eth1g_tse_mosi,
-        tse_sla_out       => eth1g_tse_miso,
-        reg_sla_in        => eth1g_reg_mosi,
-        reg_sla_out       => eth1g_reg_miso,
-        reg_sla_interrupt => eth1g_reg_interrupt,
-        ram_sla_in        => eth1g_ram_mosi,
-        ram_sla_out       => eth1g_ram_miso,
+      -- Memory Mapped Slaves
+      tse_sla_in        => eth1g_tse_mosi,
+      tse_sla_out       => eth1g_tse_miso,
+      reg_sla_in        => eth1g_reg_mosi,
+      reg_sla_out       => eth1g_reg_miso,
+      reg_sla_interrupt => eth1g_reg_interrupt,
+      ram_sla_in        => eth1g_ram_mosi,
+      ram_sla_out       => eth1g_ram_miso,
   
-        -- PHY interface
-        eth_txp           => ETH_SGOUT(0),
-        eth_rxp           => ETH_SGIN(0),
+      -- PHY interface
+      eth_txp           => ETH_SGOUT(0),
+      eth_rxp           => ETH_SGIN(0),
   
-        -- LED interface
-        tse_led           => eth1g_led
-      );
-    END GENERATE;
+      -- LED interface
+      tse_led           => eth1g_led
+    );
+  END GENERATE;
   
 END str;