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Commit 8235dc62 authored by Eric Kooistra's avatar Eric Kooistra
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Support c_cable_delay.

parent 33572b06
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1 merge request!389Resolve L2SDP-1013
Pipeline #74603 passed
...@@ -29,17 +29,17 @@ ...@@ -29,17 +29,17 @@
-- in the bsn_aligner_v2 at each node. -- in the bsn_aligner_v2 at each node.
-- --
-- . Block diagram: -- . Block diagram:
-- * tb can use one instance of tr_10Gbe to model Rx from ring and Tx to ring
-- * Ring lane serial links for ring nodes RN = 0 to c_last_rn:
-- --
-- ring lane serial links for ring nodes RN = 0 to c_last_rn: -- tr_10gbe_ring_serial_tx_arr --> tr_10gbe_ring_serial_rx_arr after c_cable_delay
--
-- tr_10gbe_ring_serial_tx_arr --> tr_10gbe_ring_serial_rx_arr
-- --
-- /<-------------------------------------------------------------\ -- /<-------------------------------------------------------------\
-- \---> 0 ---> RN - 1 ---> RN ---> RN + 1 ---> c_last_rn --->/ -- \---> 0 ---> RN - 1 ---> RN ---> RN + 1 ---> c_last_rn --->/
-- | ^ -- | ^
-- tr_10gbe_ring_serial_tx_arr(RN) | | tr_10gbe_ring_serial_tx_arr(RN) -- tr_10gbe_ring_serial_tx_arr(RN) | | tr_10gbe_ring_serial_tx_arr(RN)
-- v | -- v |
-- tr10Gbe -- tr_10Gbe
-- | ^ -- | ^
-- tr_10gbe_ring_rx_sosi_arr(RN) | | tr_10gbe_ring_tx_sosi_arr(RN) -- tr_10gbe_ring_rx_sosi_arr(RN) | | tr_10gbe_ring_tx_sosi_arr(RN)
-- v | -- v |
...@@ -69,7 +69,7 @@ use work.tb_sdp_pkg.all; ...@@ -69,7 +69,7 @@ use work.tb_sdp_pkg.all;
entity tb_sdp_beamformer_remote_ring is entity tb_sdp_beamformer_remote_ring is
generic ( generic (
g_nof_rn : natural := 16 -- number of nodes in the ring g_nof_rn : natural := 3 -- number of nodes in the ring
); );
end tb_sdp_beamformer_remote_ring; end tb_sdp_beamformer_remote_ring;
...@@ -78,6 +78,11 @@ architecture tb of tb_sdp_beamformer_remote_ring is ...@@ -78,6 +78,11 @@ architecture tb of tb_sdp_beamformer_remote_ring is
constant c_mm_clk_period : time := 1 ns; -- fast MM clk to speed up simulation constant c_mm_clk_period : time := 1 ns; -- fast MM clk to speed up simulation
constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
-- Apply cable delay in tech_pll_clk_156_period units, to remain aligned with tr_10GbE sim model
-- Choose c_cable_delay = 30 * 6.4 ~= 192 ns ~= 38 dp_clk of 5 ns, to match delay seen on HW
constant c_clk_156_period : time := tech_pll_clk_156_period; -- 6.400020 ns ~= 156.25 MHz
constant c_cable_delay : time := c_clk_156_period * 30;
-- BF data -- BF data
constant c_block_period : natural := c_sdp_N_fft; constant c_block_period : natural := c_sdp_N_fft;
constant c_block_size : natural := c_sdp_S_sub_bf * c_sdp_N_pol_bf; constant c_block_size : natural := c_sdp_S_sub_bf * c_sdp_N_pol_bf;
...@@ -107,6 +112,9 @@ architecture tb of tb_sdp_beamformer_remote_ring is ...@@ -107,6 +112,9 @@ architecture tb of tb_sdp_beamformer_remote_ring is
constant c_validate_channel_mode : string := "="; constant c_validate_channel_mode : string := "=";
constant c_sync_timeout : natural := c_block_period * (c_nof_blocks_per_sync + 1); constant c_sync_timeout : natural := c_block_period * (c_nof_blocks_per_sync + 1);
-- Timeout tb if there is no output bf_sum_sosi
constant c_tb_timeout : time := (c_nof_sync + 1) * c_sync_timeout * c_dp_clk_period;
-- Address widths of a single MM instance -- Address widths of a single MM instance
constant c_addr_w_reg_ring_lane_info_bf : natural := 1; constant c_addr_w_reg_ring_lane_info_bf : natural := 1;
...@@ -256,7 +264,7 @@ begin ...@@ -256,7 +264,7 @@ begin
v_offset := 6 + RN * v_span; v_offset := 6 + RN * v_span;
proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_cipo, reg_bsn_monitor_v2_ring_rx_bf_copi); proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_cipo, reg_bsn_monitor_v2_ring_rx_bf_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk); proc_mem_mm_bus_rd_latency(1, mm_clk);
FPGA_bf_ring_rx_latency_R(RN) <= TO_UINT(reg_bsn_monitor_v2_ring_rx_bf_cipo.rddata(c_word_w - 1 downto 0)); FPGA_bf_ring_rx_latency_R(RN) <= TO_SINT(reg_bsn_monitor_v2_ring_rx_bf_cipo.rddata(c_word_w - 1 downto 0));
end loop; end loop;
mm_init <= '0'; mm_init <= '0';
...@@ -275,6 +283,7 @@ begin ...@@ -275,6 +283,7 @@ begin
wait; wait;
end process; end process;
proc_common_timeout_failure(c_tb_timeout, tb_end); -- ERROR: end simulation if it fails to end in time
proc_common_stop_simulation(tb_end); -- OK: end simulation proc_common_stop_simulation(tb_end); -- OK: end simulation
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -283,10 +292,10 @@ begin ...@@ -283,10 +292,10 @@ begin
gen_dut : for RN in 0 to c_last_rn generate gen_dut : for RN in 0 to c_last_rn generate
-- Connect ring wires between the nodes -- Connect ring wires between the nodes
wire_ring : if RN > 0 generate wire_ring : if RN > 0 generate
tr_10gbe_ring_serial_rx_arr(RN) <= tr_10gbe_ring_serial_tx_arr(RN - 1); tr_10gbe_ring_serial_rx_arr(RN) <= transport tr_10gbe_ring_serial_tx_arr(RN - 1) after c_cable_delay;
end generate; end generate;
close_ring : if RN = 0 generate close_ring : if RN = 0 generate
tr_10gbe_ring_serial_rx_arr(0) <= tr_10gbe_ring_serial_tx_arr(c_last_rn); tr_10gbe_ring_serial_rx_arr(0) <= transport tr_10gbe_ring_serial_tx_arr(c_last_rn) after c_cable_delay;
end generate; end generate;
-- tr_10GbE access at each node, all via front_io QSFP[0] -- tr_10GbE access at each node, all via front_io QSFP[0]
...@@ -377,6 +386,9 @@ begin ...@@ -377,6 +386,9 @@ begin
-- Intermediate BF alignment and summation at each node -- Intermediate BF alignment and summation at each node
u_sdp_beamformer_remote : entity work.sdp_beamformer_remote u_sdp_beamformer_remote : entity work.sdp_beamformer_remote
generic map (
g_nof_aligners_max => g_nof_rn
)
port map ( port map (
dp_clk => dp_clk, dp_clk => dp_clk,
dp_rst => dp_rst, dp_rst => dp_rst,
......
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