-Added corr_adder which is used in corr_accumulator;

 .added to hdllib.cfg
-Also instantiated common_shiftrams in corr_accumulator;
-Correlator now instantiates most required stages
 .excl. corr_folder

libraries/dsp/correlator/hdllib.cfg

@@ -11,6 +11,7 @@ synth_files =
     $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
     $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
     $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd
+    $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
     $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
     $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/correlator.vhd
     $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/unb1_correlator.vhd

libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd

@@ -26,21 +26,101 @@ USE common_lib.common_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 
 -- Purpose:
+-- . Keep a running sum for each element in snk_in_arr[i]
 -- Description:
+-- . A RAM-block is used to store the running sums as wel as to output the
+--   corresponding previous running sum so both align at the adder inputs.
 
 ENTITY corr_accumulator IS
   GENERIC (
-    g_nof_inputs  : NATURAL
+    g_nof_inputs        : NATURAL;
+    g_accumulator_depth : NATURAL;
+    g_data_w        : NATURAL
    ); 
   PORT (
     rst            : IN  STD_LOGIC;
-    clk            : IN  STD_LOGIC
+    clk            : IN  STD_LOGIC;
+
+    snk_in_arr     : IN  t_dp_sosi_arr;
+    src_out_arr    : OUT t_dp_sosi_arr
   );
 END corr_accumulator;
 
 ARCHITECTURE rtl OF corr_accumulator IS
 
+  CONSTANT c_shiftram_io_delay        : NATURAL := 3; -- common_shiftram data_in takes 3 cycles to emerge as data_out
+
+  -- c_shiftram_delay is such that common_shiftram output aligns exactly with snk_in_arr. Functionally this 
+  -- means we aligned the current word to the corresponding previous word at the adder inputs.
+  CONSTANT c_shiftram_delay           : NATURAL := g_accumulator_depth-c_shiftram_io_delay;
+  CONSTANT c_shift_w                  : NATURAL := ceil_log2(g_nof_words);
+  CONSTANT c_common_shiftram_shift_in : STD_LOGIC_VECTOR := (c_shift_w-1 DOWNTO 0) := TO_UVEC(c_shiftram_delay, c_shift_w);
+
+  SIGNAL corr_adder_snk_in_2arr_2     : t_dp_sosi_2arr_2(g_nof_inputs-1 DOWNTO 0) -- Array of pairs
+  SIGNAL corr_adder_src_out_arr       : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+
+  SIGNAL common_shiftram_snk_in_arr   : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+  SIGNAL common_shiftram_src_out_arr  : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+
 BEGIN
 
+  -----------------------------------------------------------------------------
+  -- Adder inputs: current snk_in_arr + corresponding previous running sum
+  -- from shiftram
+  -----------------------------------------------------------------------------
+  gen_adder_inputs : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+    corr_adder_snk_in_2arr_2(i)(0) <= snk_in_arr(i);
+    corr_adder_snk_in_2arr_2(i)(1) <= common_shiftram_src_out_arr(i);
+  END GENERATE;
+
+  -----------------------------------------------------------------------------
+  -- Complex adder stage
+  -----------------------------------------------------------------------------
+  u_corr_adder : ENTITY work.corr_adder
+  GENERIC MAP (
+    g_nof_inputs => g_nof_inputs
+  )
+  PORT MAP (
+    clk            => clk,
+    rst            => rst,
+
+    snk_in_2arr_2  => corr_adder_snk_in_2arr_2,
+    src_out_arr    => corr_adder_src_out_arr
+  );  
+
+  -----------------------------------------------------------------------------
+  -- Write the current sum to RAM; RAM outputs delayed running sums that align
+  -- at the adder inputs:
+  -- . common_shiftram_src_out_arr = delayed corr_adder_src_out_arr
+  -----------------------------------------------------------------------------
+  -- Concatenate real&imaginary parts
+  common_shiftram_snk_in_arr(i).data(g_data_w-1   DOWNTO g_data_w/2) <= corr_adder_src_out_arr(i).re(g_data_w/2-1 DOWNTO 0);
+  common_shiftram_snk_in_arr(i).data(g_data_w/2-1 DOWNTO 0)          <= corr_adder_src_out_arr(i).im(g_data_w/2-1 DOWNTO 0);
+
+  gen_common_shiftram : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+    u_common_shiftram : ENTITY common_lib.common_shiftram
+    GENERIC MAP (
+      g_data_w    => g_data_w,
+      g_nof_words => g_accumulator_depth
+    )
+    PORT MAP (
+      rst            => rst,
+      clk            => clk,
+      
+      data_in        => common_shiftram_snk_in_arr(i).data(g_data_w-1 DOWNTO 0),
+      data_in_val    => common_shiftram_snk_in_arr(i).valid,
+      data_in_shift  => c_common_shiftram_shift_in,
+   
+      data_out       => common_shiftram_src_out_arr(i).data(g_data_w-1 DOWNTO 0),
+      data_out_val   => common_shiftram_src_out_arr(i).valid,
+      data_out_shift => OPEN
+    );
+  END GENERATE;
+
+  -----------------------------------------------------------------------------
+  -- Output 1/g_accumulator_depth words per stream
+  -- . Not implemented yet.
+  -----------------------------------------------------------------------------
+  src_out <= common_shiftram_src_out_arr;
 
 END rtl;

libraries/dsp/correlator/src/vhdl/corr_adder.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+-- Purpose:
+-- . Provide an array of complex adders with streaming I/O
+-- Description:
+-- . Adds snk_in_2arr_2[i][0] to snk_in_2arr_2[i][1] yielding 
+--   src_out_2arr[i] for i in 0..g_nof_inputs-1.
+
+ENTITY corr_adder IS
+  GENERIC (
+    g_nof_inputs  : NATURAL
+   ); 
+  PORT (
+    rst            : IN  STD_LOGIC;
+    clk            : IN  STD_LOGIC;
+
+    snk_in_2arr_2  : IN  t_dp_sosi_2arr_2(g_nof_inputs);
+
+    src_out_2arr   : OUT t_dp_sosi_2arr_2(g_nof_inputs)
+  );
+END corr_adder;
+
+ARCHITECTURE str OF corr_adder IS
+
+BEGIN
+
+  gen_common_complex_add_sub : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+    u_common_complex_add_sub : ENTITY common_lib.common_complex_add_sub
+    GENERIC MAP (
+      g_direction       => "ADD",
+      g_representation  => "SIGNED",
+      g_pipeline_input  => 0,
+      g_pipeline_output => 1,
+      g_in_dat_w        => 36,
+      g_out_dat_w       => 64
+    )
+    PORT MAP (
+      clk        => clk,
+      in_ar      => snk_in_2arr_2(i)(0).re(35 DOWNTO 0),
+      in_ai      => snk_in_2arr_2(i)(0).im(35 DOWNTO 0),
+      in_br      => snk_in_2arr_2(i)(1).re(35 DOWNTO 0),
+      in_bi      => snk_in_2arr_2(i)(1).im(35 DOWNTO 0),
+      out_re     => src_out_2arr(i).re(63 DOWNTO 0),
+      out_im     => src_out_2arr(i).im(63 DOWNTO 0)
+    );     
+  END GENERATE;
+
+END str;

libraries/dsp/correlator/src/vhdl/correlator.vhd

@@ -26,21 +26,82 @@ USE common_lib.common_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 
 -- Purpose:
+-- . Calculate the cross- and auto correlations of g_nof_inputs inputs.
 -- Description:
+-- . 
 
 ENTITY correlator IS
   GENERIC (
-    g_nof_inputs  : NATURAL
+    g_nof_inputs  : NATURAL;
+    g_nof_mults   : NATURAL
    ); 
   PORT (
     rst            : IN  STD_LOGIC;
-    clk            : IN  STD_LOGIC
+    clk            : IN  STD_LOGIC;
+
+    snk_in_arr     : IN  t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+
+
   );
 END correlator;
 
-ARCHITECTURE rtl OF correlator IS
+ARCHITECTURE str OF correlator IS
+
+  SIGNAL corr_permutator_src_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs*(g_nof_inputs+1)/2-1 DOWNTO 0) -- Array of pairs
+  SIGNAL corr_multiplier_src_out_arr    : t_dp_sosi_arr(g_nof_mults-1 DOWNTO 0);
+  SIGNAL corr_accumulator_src_out_arr   : t_dp_sosi_arr(g_nof_mults-1 DOWNTO 0);
 
 BEGIN
 
+  -----------------------------------------------------------------------------
+  -- Create all unique pair permutations of the input streams
+  -----------------------------------------------------------------------------
+  u_corr_permutator : ENTITY work.corr_permutator
+  GENERIC MAP (
+    g_nof_inputs => g_nof_inputs
+  )
+  PORT MAP (
+    clk            => clk,
+    rst            => rst,
+
+    snk_in_arr     => snk_in_arr,
+    src_out_2arr_2 => corr_permutator_src_out_2arr_2
+  );     
+
+  -----------------------------------------------------------------------------
+  -- Fold the streams if g_nof_mults < g_nof_inputs
+  -- . Folder not implemented yet; section bypassed.
+  -----------------------------------------------------------------------------
+  corr_folder_src_out_2arr_2 <= corr_permutator_src_out_2arr_2;
+
+  -----------------------------------------------------------------------------
+  -- Complex multiplier stage
+  -----------------------------------------------------------------------------
+  u_corr_multiplier : ENTITY work.corr_multiplier
+  GENERIC MAP (
+    g_nof_inputs => g_nof_mults
+  )
+  PORT MAP (
+    clk            => clk,
+    rst            => rst,
+
+    snk_in_2arr_2  => corr_folder_src_out_2arr_2,
+    src_out_arr    => corr_multiplier_src_out_arr
+  );  
+
+  -----------------------------------------------------------------------------
+  -- Accumulator stage
+  -----------------------------------------------------------------------------
+  u_corr_accumulator : ENTITY work.corr_accumulator
+  GENERIC MAP (
+    g_nof_inputs => g_nof_mults
+  )
+  PORT MAP (
+    clk            => clk,
+    rst            => rst,
+
+    snk_in_arr     => corr_multiplier_src_out_arr,
+    src_out_arr    => corr_accumulator_src_out_arr
+  );
 
-END rtl;
+END str;