Add some notes for sdp_requantization talk.

doc/erko_teaser_talks.txt

@@ -107,6 +107,14 @@ at university.
   . similar for a % b to get remainder after division by b
     side note: beware of a % b == 1, result is language dependent when a or b is negative
 
+* internal processing uses more LSbits --> rounding needed
+  output has reduced RFI --> clipping needed
+
+
+* Integers represent fixed point values:
+Fixed point values represent floating-point values, with exponent (position of the point) fixed at compile time
+Position of the point is implicit or defined by constants at compile time
+Number of bits of integer corresponds to number of bits of the mantissa in floating point
 
 * Removing LSbits (unused resolution, insignificant bits)
   - truncation by discarding LSbit is free in logic:
@@ -130,6 +138,17 @@ at university.
       +1 0001   0 00
        0 0000   0 00
 
+    . E.g. 3 bit value discard 1 LSbit
+
+      -1 111  -1 11
+      -2 110  -1 11
+      -3 101  -2 10
+      -4 100  -2 10
+      +3 011   1 01
+      +2 010   1 01
+      +1 001   0 00
+       0 000   0 00
+
     Corresponds to:
     . shift right by n bits >> : -5 >> 2 = -2, 5 >> 2 = 1
     . divide // 2**n : -5 // 4 = -2, 5 // 4 = 1
@@ -174,6 +193,20 @@ at university.
   - supports removing MSbits and LSbits
   - to ensure same Q scheme is used consistently throughout the SDP firmware
 
+entity dp_requantize is
+  generic (
+    g_representation      : string  := "SIGNED";
+    g_lsb_w               : integer := 4;
+    g_lsb_round           : boolean := true;
+    g_lsb_round_clip      : boolean := false;
+    g_lsb_round_even      : boolean := true;  -- else away
+    g_msb_clip            : boolean := true;  -- else wrap
+    g_msb_clip_symmetric  : boolean := false;
+
+    g_in_dat_w            : natural := 36;  -- input data width
+    g_out_dat_w           : natural := 18  -- output data width
+  );
+
 
 * SDP signal path
   - Task: Preserve sensitivity of the ADC input and maintain sufficient dynamic range
@@ -203,7 +236,7 @@ at university.
 
     The RFI sets the maximum input level for the ADC --> -50 dBFS margin to avoid overflow (clipping)
 
-    Used FPGA build in multipliers of 18b * 18b or 27b * 18b
+    Used FPGA build in multipliers of 18b * 18b or 27b * 27b
 
     FIR filter
     - Consists of multiply (real coefficients) accumulates (taps)