Use c_blocks_per_sync = 16 in simulation.

boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd

@@ -106,7 +106,7 @@ ARCHITECTURE str OF unb1_ddr3_transpose IS
   CONSTANT c_nof_streams             : POSITIVE := 4;  
   CONSTANT c_frame_size_in           : POSITIVE := c_wr_chunksize;
   CONSTANT c_frame_size_out          : POSITIVE := c_frame_size_in;      
-  CONSTANT c_nof_blk_per_sync        : POSITIVE := 1600000;     
+  CONSTANT c_nof_blk_per_sync        : POSITIVE := sel_a_b(g_sim, 16, 1600000);
   CONSTANT c_ena_pre_transpose       : BOOLEAN  := FALSE; 
  
   -- Custom definitions of constants

boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/tc_unb_ddr3_transpose.py

@@ -92,6 +92,9 @@ c_pagesize          = c_blocksize * g_nof_blocks
 c_bg_nof_streams    = 4 
 c_bg_ram_size       = g_wr_chunksize * g_wr_nof_chunks * g_rd_chunksize
 c_in_dat_w          = 8
+if tc.sim==True:
+    c_blocks_per_sync   = 16
+else:
     c_blocks_per_sync   = 1600000
 c_db_nof_streams    = c_bg_nof_streams
 c_db_ram_size       = c_bg_ram_size #g_rd_chunksize * g_rd_nof_chunks * g_nof_blocks