-Added support for weights registers instead of RAM blocks to beamformer.

 . Added TB instances to tb_tb_beamformer to test the register version as well
 . reverified (OK) using tb_tb_beamformer.
-Now using weight registers in arts_tab_beamformer instead of RAM.
 . reverified (OK) using tb_tb_arts_tab_beamformer.

applications/arts/libraries/arts_tab_beamformer/src/vhdl/arts_tab_beamformer.vhd

@@ -182,7 +182,9 @@ BEGIN
       g_weights_w             => g_weights_w,
       g_weights_file          => sel_a_b(g_weights_file="UNUSED", "UNUSED", g_weights_file & "_" & NATURAL'IMAGE(i)),
       g_weights_ram_dual_port => g_weights_ram_dual_port,
-      g_mult_variant          => g_mult_variant
+      g_mult_variant          => g_mult_variant,
+      g_use_weight_ram        => FALSE,
+      g_use_weight_reg        => TRUE -- Use registers instead of RAM
     )
     PORT MAP (
       dp_clk      => dp_clk,
@@ -200,8 +202,6 @@ BEGIN
       src_out     => beamformer_src_out_arr(i)
     );  
 
-    
-
     ------------------------------------------------------------------------------
     -- Requantize the outputs to the desired bit width
     ------------------------------------------------------------------------------

libraries/dsp/beamformer/src/vhdl/beamformer.vhd

@@ -35,6 +35,11 @@
 --   . Input/output reordering and quantization are also application 
 --     specific and should be done in the wrapper.
 -- . The input array snk_in_arr must be synchronous.
+-- . If RAM is not desired, set g_use_weight_reg or g_use_weight_arr.
+--   . The addressing remains the same (done using weight_addr) but the
+--     source of the weights can be selected that way.
+-- . Note: Only set 1 of g_use_weight_ram, g_use_weight_reg, g_use_weight_arr
+--         to TRUE.
 
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.ALL;
@@ -53,8 +58,11 @@ ENTITY beamformer IS
     g_nof_weights           : NATURAL;
     g_weights_w             : NATURAL := 16;
     g_weights_file          : STRING  := "hex/beamformer_weights";
-    g_weights_ram_dual_port : BOOLEAN := TRUE;
-    g_mult_variant          : STRING := "IP"
+    g_weights_ram_dual_port : BOOLEAN := TRUE; --FIXME rename this to readback_weights
+    g_mult_variant          : STRING := "IP";
+    g_use_weight_ram        : BOOLEAN := TRUE;  -- Use weights RAM (default)
+    g_use_weight_reg        : BOOLEAN := FALSE; -- Use a weights register instead of RAM
+    g_use_weight_arr        : BOOLEAN := FALSE  -- Use the input weights array instead of weights RAM of Registers
   );
   PORT (
     dp_clk      : IN  STD_LOGIC; 
@@ -63,10 +71,11 @@ ENTITY beamformer IS
     mm_clk      : IN  STD_LOGIC;
     mm_rst      : IN  STD_LOGIC;
 
-    ram_mosi    : IN  t_mem_mosi := c_mem_mosi_rst; -- MM interface to upload weights to RAM
+    ram_mosi    : IN  t_mem_mosi := c_mem_mosi_rst; -- MM interface to upload weights to RAM or REG
     ram_miso    : OUT t_mem_miso;
 
-    weight_addr : IN  STD_LOGIC_VECTOR(ceil_log2(g_nof_weights)-1 DOWNTO 0); -- Weight RAM address
+    weight_addr : IN  STD_LOGIC_VECTOR(ceil_log2(g_nof_weights)-1 DOWNTO 0); -- Weight address
+    weight_arr  : IN  t_slv_32_arr(g_nof_inputs-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
    
     snk_in_arr  : IN  t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0); -- All streams must be synchronous
     src_out     : OUT t_dp_sosi
@@ -97,6 +106,20 @@ ARCHITECTURE str OF beamformer IS
  
   SIGNAL common_ram_crw_crw_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
 
+  ------------------------------------------------------------------------------
+  -- Weights REG
+  ------------------------------------------------------------------------------
+  TYPE t_common_reg_r_d_dc_out_slv_arr IS ARRAY(g_nof_inputs-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_common_ram_crw_crw_ram.dat_w*c_common_ram_crw_crw_ram.nof_dat-1 DOWNTO 0);
+  TYPE t_common_reg_r_d_dc_out_arr     IS ARRAY(g_nof_weights-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_common_ram_crw_crw_ram.dat_w-1 DOWNTO 0);
+  TYPE t_common_reg_r_d_dc_out_2arr    IS ARRAY(g_nof_inputs-1 DOWNTO 0) OF t_common_reg_r_d_dc_out_arr;
+
+  SIGNAL common_reg_r_w_dc_in_reg_slv_arr  : t_common_reg_r_d_dc_out_slv_arr;
+  SIGNAL common_reg_r_w_dc_out_reg_slv_arr : t_common_reg_r_d_dc_out_slv_arr;
+  SIGNAL common_reg_r_w_dc_out_reg_2arr    : t_common_reg_r_d_dc_out_2arr;
+
+  -- The register outputs the weight 1 cycle too soon relative to the RAM, so register the address
+  SIGNAL reg_weight_addr :  STD_LOGIC_VECTOR(ceil_log2(g_nof_weights)-1 DOWNTO 0);
+
   ------------------------------------------------------------------------------
   -- Pipeline 
   ------------------------------------------------------------------------------
@@ -113,6 +136,7 @@ BEGIN
   ------------------------------------------------------------------------------
   -- Weights RAM
   ------------------------------------------------------------------------------
+  gen_weight_ram : IF g_use_weight_ram = TRUE GENERATE
     gen_common_ram_crw_crw : FOR i IN 0 TO g_nof_inputs-1 GENERATE
   
       -- Read request on every incoming valid cycle
@@ -155,8 +179,58 @@ BEGIN
       common_ram_crw_crw_src_out_arr(i).valid <= common_ram_crw_crw_rd_val_b_arr(i);
   
     END GENERATE;
+  END GENERATE;
 
-  -- Combine the individual RAM MM buses into one
+  ------------------------------------------------------------------------------
+  -- Weights register
+  ------------------------------------------------------------------------------
+  gen_weight_reg : IF g_use_weight_reg = TRUE GENERATE
+    gen_common_reg_r_w_dc : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+  
+      u_common_reg_r_w_dc : ENTITY common_lib.common_reg_r_w_dc
+      GENERIC MAP (
+        g_cross_clock_domain => TRUE,
+        g_readback           => g_weights_ram_dual_port,
+        g_reg                => c_common_ram_crw_crw_ram
+      )
+      PORT MAP (
+        -- Clocks and reset
+        mm_rst         => mm_rst,
+        mm_clk         => mm_clk,
+        st_rst         => dp_rst,
+        st_clk         => dp_clk,
+    
+        -- Memory Mapped Slave in mm_clk domain
+        sla_in         => ram_mosi_arr(i),
+        sla_out        => ram_miso_arr(i),
+    
+        -- MM registers in st_clk domain
+        reg_wr_arr     => open,
+        reg_rd_arr     => open,
+        in_reg         => common_reg_r_w_dc_in_reg_slv_arr(i),  
+        out_reg        => common_reg_r_w_dc_out_reg_slv_arr(i)
+      );
+  
+      -- Rewire the concatenated SLV array to something we can index properly [g_nof_inputs][g_nof_weights]
+      gen_common_reg_r_w_dc_out_reg_2arr : FOR j IN 0 TO g_nof_weights-1 GENERATE
+        common_reg_r_w_dc_out_reg_2arr(i)(j) <= common_reg_r_w_dc_out_reg_slv_arr(i)(j*2*g_weights_w+2*g_weights_w-1 DOWNTO j*2*g_weights_w);
+      END GENERATE;
+
+      -- REG output rewired to 'RAM' SOSI array. The weight is indexed by reg_weight_addr. 
+      common_ram_crw_crw_src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_reg_r_w_dc_out_reg_2arr(i)(TO_UINT(reg_weight_addr))(  g_weights_w-1 DOWNTO 0));
+      common_ram_crw_crw_src_out_arr(i).im <= RESIZE_DP_DSP_DATA(common_reg_r_w_dc_out_reg_2arr(i)(TO_UINT(reg_weight_addr))(2*g_weights_w-1 DOWNTO g_weights_w));
+
+    END GENERATE; 
+
+    gen_readback: IF g_weights_ram_dual_port=TRUE GENERATE
+      common_reg_r_w_dc_in_reg_slv_arr <= common_reg_r_w_dc_out_reg_slv_arr;
+    END GENERATE;
+
+  END GENERATE; 
+
+  ------------------------------------------------------------------------------
+  -- Combine the individual MM buses into one
+  ------------------------------------------------------------------------------
   u_common_mem_mux : ENTITY common_lib.common_mem_mux
   GENERIC MAP (    
     g_nof_mosi    => g_nof_inputs,
@@ -224,4 +298,16 @@ BEGIN
     src_out    => src_out
   );
 
+  ------------------------------------------------------------------------------
+  -- Registers
+  ------------------------------------------------------------------------------
+  p_clk : PROCESS(dp_rst, dp_clk)
+  BEGIN
+    IF dp_rst='1' THEN
+      reg_weight_addr <= (OTHERS=>'0');
+    ELSIF rising_edge(dp_clk) THEN
+      reg_weight_addr <= weight_addr;
+    END IF;
+  END PROCESS;
+
 END str; 

libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd

@@ -46,7 +46,9 @@ ENTITY tb_beamformer IS
     --g_technology     : NATURAL := c_tech_select_default;
     g_nof_inputs     : NATURAL := 2;
     g_nof_weights    : NATURAL := 32;
-    g_data_w       : NATURAL := 8   --8b complex input data
+    g_data_w         : NATURAL := 8;  --8b complex input data
+    g_use_weight_ram : BOOLEAN := FALSE;
+    g_use_weight_reg : BOOLEAN := TRUE
   );
 END tb_beamformer;
 
@@ -281,9 +283,9 @@ ARCHITECTURE tb OF tb_beamformer IS
 
     proc_common_wait_some_cycles(dp_clk, 1);
     IF OK = '0' THEN
-      REPORT "TEST WENT WRONG.";
+      REPORT "TEST FAILED.";
     ELSE
-      REPORT "Test succesfull ended.";
+      REPORT "Test passed.";
     END IF;
 
     tb_end <= '1';  -- end test
@@ -306,7 +308,9 @@ ARCHITECTURE tb OF tb_beamformer IS
     g_nof_inputs     => g_nof_inputs,
     g_nof_weights    => g_nof_weights,
     g_data_w         => g_data_w,
-    g_weights_file => "UNUSED"
+    g_weights_file   => "UNUSED",
+    g_use_weight_ram => g_use_weight_ram,
+    g_use_weight_reg => g_use_weight_reg
   )
   PORT MAP (
     dp_clk      => dp_clk,

libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd

@@ -46,12 +46,19 @@ BEGIN
 --  --g_technology   : NATURAL := c_tech_select_default;
 --  g_nof_inputs     : NATURAL := 2;
 --  g_nof_weights    : NATURAL := 32;
---  g_data_w       : NATURAL := 8   --8b complex input data
+--  g_data_w         : NATURAL := 8;   --8b complex input data
+--  g_use_weight_ram : BOOLEAN := FALSE;
+--  g_use_weight_reg : BOOLEAN := TRUE
 --
 
 -- do test for different number of inputs
-sim_i1_beamformer   : ENTITY work.tb_beamformer GENERIC MAP (1, 1, 32, 8);
-sim_i2_beamformer   : ENTITY work.tb_beamformer GENERIC MAP (2, 2, 32, 8);
-sim_i32_beamformer   : ENTITY work.tb_beamformer GENERIC MAP (3, 32, 32, 8);
+-- . (weights in RAM)
+sim_i01_ram_beamformer : ENTITY work.tb_beamformer GENERIC MAP (1,  1, 32, 8, TRUE, FALSE);
+sim_i02_ram_beamformer : ENTITY work.tb_beamformer GENERIC MAP (2,  2, 32, 8, TRUE, FALSE);
+sim_i32_ram_beamformer : ENTITY work.tb_beamformer GENERIC MAP (3, 32, 32, 8, TRUE, FALSE);
+-- . (weights in Registers)
+sim_i01_reg_beamformer : ENTITY work.tb_beamformer GENERIC MAP (4,  1, 32, 8, FALSE, TRUE);
+sim_i02_reg_beamformer : ENTITY work.tb_beamformer GENERIC MAP (5,  2, 32, 8, FALSE, TRUE);
+sim_i32_reg_beamformer : ENTITY work.tb_beamformer GENERIC MAP (6, 32, 32, 8, FALSE, TRUE);
 
 END tb;