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Commit 7f851b8e authored by Pepping's avatar Pepping
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- Updated port map of DUT. 

- Added io_ddr to the testbench after removing it from the DUT.
parent 8f810e64
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libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
+ 118
− 36
View file @ 7f851b8e
......@@ -56,7 +56,9 @@ ENTITY tb_reorder_transpose IS
g_rd_nof_chunks : POSITIVE := 4;
g_gapsize : NATURAL := 0;
g_nof_blocks : POSITIVE := 4;
g_nof_blk_per_sync : POSITIVE := 64
g_nof_blk_per_sync : POSITIVE := 64;
g_nof_streams : POSITIVE := 4;
g_in_dat_w : POSITIVE := 8
);
END tb_reorder_transpose;
......@@ -78,6 +80,8 @@ ARCHITECTURE tb OF tb_reorder_transpose IS
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC := '0';
SIGNAL dp_rst_in : STD_LOGIC;
SIGNAL dp_clk_in : STD_LOGIC := '0';
----------------------------------------------------------------------------
-- MM buses
......@@ -129,12 +133,23 @@ ARCHITECTURE tb OF tb_reorder_transpose IS
g_gapsize,
g_nof_blocks);
CONSTANT c_blocksize : POSITIVE := g_wr_nof_chunks * g_wr_chunksize;
CONSTANT c_page_size : POSITIVE := c_blocksize * g_nof_blocks;
CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
CONSTANT c_data_w : NATURAL := 64;
CONSTANT c_min_fifo_size : POSITIVE := 256;
CONSTANT c_blocksize : POSITIVE := c_reorder_seq.wr_nof_chunks * (c_reorder_seq.wr_chunksize + c_reorder_seq.gapsize);
CONSTANT c_pagesize : POSITIVE := c_reorder_seq.nof_blocks * c_blocksize;
CONSTANT c_mem_size : POSITIVE := 2*c_pagesize;
CONSTANT c_mem_size_w : POSITIVE := ceil_log2(c_mem_size);
CONSTANT c_wr_fifo_depth : NATURAL := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);--c_blocksize * 2;
CONSTANT c_rd_fifo_depth : NATURAL := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);--c_blocksize * 2;
CONSTANT c_use_complex : BOOLEAN := TRUE;
CONSTANT c_total_data_w : NATURAL := g_nof_streams*g_in_dat_w;
CONSTANT c_complex_data_w : NATURAL := c_total_data_w*c_nof_complex;
CONSTANT c_data_w : NATURAL := sel_a_b(c_use_complex, c_complex_data_w, c_total_data_w);
CONSTANT c_ctrl_ref_clk_period : TIME := 5000 ps;
......@@ -143,14 +158,14 @@ ARCHITECTURE tb OF tb_reorder_transpose IS
CONSTANT c_db_block_len : NATURAL := c_blocksize * g_rd_chunksize;
-- Configuration of the block generator:
CONSTANT c_bg_nof_output_streams : POSITIVE := 4;
CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*8;
CONSTANT c_bg_nof_output_streams : POSITIVE := g_nof_streams;
CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*g_in_dat_w;
CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_len);
CONSTANT c_bg_data_file_prefix : STRING := "UNUSED"; -- "../../../src/hex/tb_bg_dat";
CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
-- Configuration of the databuffers:
CONSTANT c_db_nof_streams : POSITIVE := 4;
CONSTANT c_db_nof_streams : POSITIVE := g_nof_streams;
CONSTANT c_db_data_w : POSITIVE := c_diag_db_max_data_w;
CONSTANT c_db_buf_nof_data : POSITIVE := c_db_block_len;
CONSTANT c_db_buf_use_sync : BOOLEAN := FALSE;
......@@ -163,11 +178,20 @@ ARCHITECTURE tb OF tb_reorder_transpose IS
SIGNAL out_sosi_arr : t_dp_sosi_arr(c_bg_nof_output_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL out_siso_arr : t_dp_siso_arr(c_bg_nof_output_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- Signals to interface with the DDR3 memory model.
-- Signals to interface with the DDR conroller and memory model.
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL to_mem_sosi : t_dp_sosi;
SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL from_mem_sosi : t_dp_sosi;
SIGNAL phy_in : t_tech_ddr_phy_in;
SIGNAL phy_io : t_tech_ddr_phy_io;
SIGNAL phy_ou : t_tech_ddr_phy_ou;
BEGIN
----------------------------------------------------------------------------
......@@ -176,8 +200,8 @@ BEGIN
mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
dp_clk_in <= NOT dp_clk_in AFTER c_dp_clk_period/2;
dp_rst_in <= '1', '0' AFTER c_dp_clk_period*5;
------------------------------------------------------------------------------
-- External PPS
......@@ -249,14 +273,13 @@ BEGIN
u_dut: ENTITY work.reorder_transpose
GENERIC MAP(
g_sim => c_sim,
g_technology => c_tech_select_default,
g_tech_ddr => c_tech_ddr,
g_nof_streams => c_bg_nof_output_streams,
g_in_dat_w => c_bg_buf_dat_w/c_nof_complex,
g_frame_size_in => g_wr_chunksize,
g_frame_size_out => g_wr_chunksize,
g_nof_blk_per_sync => g_nof_blk_per_sync,
g_use_complex => TRUE,
g_use_complex => c_use_complex,
g_ena_pre_transp => FALSE,
g_reorder_seq => c_reorder_seq_conf
)
......@@ -267,8 +290,10 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
-- ST sink
snk_out_arr => bg_siso_arr,
snk_in_arr => bg_sosi_arr,
-- ST source
src_in_arr => out_siso_arr,
src_out_arr => out_sosi_arr,
......@@ -276,11 +301,68 @@ BEGIN
ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
ser_term_ctrl_out => OPEN,
par_term_ctrl_out => OPEN,
-- Control interface to the external memory
dvr_miso => ctlr_dvr_miso,
dvr_mosi => ctlr_dvr_mosi,
-- Data interface to the external memory
to_mem_src_out => to_mem_sosi,
to_mem_src_in => to_mem_siso,
from_mem_snk_in => from_mem_sosi,
from_mem_snk_out => from_mem_siso
);
u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
GENERIC MAP(
g_sim => c_sim,
g_technology => c_tech_select_default, -- : NATURAL := c_tech_select_default;
g_tech_ddr => c_tech_ddr, -- : t_c_tech_ddr;
g_cross_domain_dvr_ctlr => FALSE, --TRUE, -- : BOOLEAN := TRUE;
g_wr_data_w => c_data_w, -- : NATURAL := 32;
g_wr_fifo_depth => c_wr_fifo_depth, -- : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
g_rd_fifo_depth => c_rd_fifo_depth, -- : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
g_rd_data_w => c_data_w, -- : NATURAL := 32;
g_wr_flush_mode => "SYN", -- : STRING := "VAL"; -- "VAL", "SOP", "SYN"
g_wr_flush_use_channel => FALSE, -- : BOOLEAN := FALSE;
g_wr_flush_start_channel => 0, -- : NATURAL := 0;
g_wr_flush_nof_channels => 1 -- : POSITIVE := 1
)
PORT MAP (
-- DDR reference clock
ctlr_ref_clk => dp_clk_in,
ctlr_ref_rst => dp_rst_in,
-- DDR controller clock domain
ctlr_clk_out => dp_clk, -- output clock of the ddr controller is used as DP clk.
ctlr_rst_out => dp_rst,
ctlr_clk_in => dp_clk,
ctlr_rst_in => dp_rst,
-- Driver clock domain
dvr_clk => dp_clk,
dvr_rst => dp_rst,
dvr_miso => ctlr_dvr_miso,
dvr_mosi => ctlr_dvr_mosi,
-- Write FIFO clock domain
wr_clk => dp_clk,
wr_rst => dp_rst,
wr_fifo_usedw => OPEN,
wr_sosi => to_mem_sosi,
wr_siso => to_mem_siso,
-- Read FIFO clock domain
rd_clk => dp_clk,
rd_rst => dp_rst,
ser_term_ctrl_in => OPEN,
par_term_ctrl_in => OPEN,
rd_fifo_usedw => OPEN,
rd_sosi => from_mem_sosi,
rd_siso => from_mem_siso,
phy_in => phy_in,
phy_io => phy_io,
......
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