Merge master.

applications/lofar2/images/images.txt

@@ -11,5 +11,7 @@ lofar2_unb2b_sdp_station_xsub_one-r087d98be6        | 2021-06-14    | R vd Walle
 unb2b_minimal-rce6b96eed                            | 2021-08-26    | P. Donker            | unb2b_minimal with new mmap, rbf maid with option --unb2_factory
 lofar2_unb2b_sdp_station_full-r9ff51058a            | 2022-01-12    | R vd Walle           | Old Lofar2 SDP station full design for UniBoard2b without ring.
 lofar2_unb2b_sdp_station_full-r2c3958e1f            | 2022-04-29    | R vd Walle           | Lofar2 SDP station full design for UniBoard2b.
-lofar2_unb2b_sdp_station_full_wg-r70b28ffc3         | 2022-06-15    | R vd Walle           | Lofar2 SDP station design without ADC inputs, only WG. Uses dp_clk + dp_pps instead of rx_clk + rx_sysref.
-lofar2_unb2c_sdp_station_full-r70484fd08            | 2022-04-29    | R vd Walle           | Lofar2 SDP station full design for UniBoard2c.
+lofar2_unb2b_sdp_station_full_wg-r70b28ffc3         | 2022-06-15    | R vd Walle           | Do not use, has beamlet/subband weight bug, delete when r01205cbe4 is OK.
+lofar2_unb2b_sdp_station_full_wg-r01205cbe4         | 2022-07-14    | R vd Walle           | Lofar2 SDP station design without ADC inputs, only WG. Uses dp_clk + dp_pps instead of rx_clk + rx_sysref.
+lofar2_unb2c_sdp_station_full-r70484fd08            | 2022-04-29    | R vd Walle           | Do not use, has beamlet/subband weight bug, delete when r01205cbe4 is OK.
+lofar2_unb2c_sdp_station_full-r01205cbe4            | 2022-07-14    | R vd Walle           | Lofar2 SDP station full design for UniBoard2c.

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd

@@ -325,7 +325,7 @@ BEGIN
     g_use_mm_output           => TRUE,   
     g_rd_latency              => 1, -- Required for st_xst 
     -- for mms_dp_bsn_monitor_v2
-    g_nof_clk_per_sync        => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
+    g_nof_clk_per_sync        => c_sdp_N_clk_sync_timeout_xsub, -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
     g_nof_input_bsn_monitors  => g_P_sq,  
     g_use_bsn_output_monitor  => TRUE  
     )
@@ -439,7 +439,8 @@ BEGIN
     g_statistics_type          => "XST",
     g_offload_time             => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
     g_P_sq                     => g_P_sq,
-    g_crosslets_direction => 1  -- = lane direction
+    g_crosslets_direction      => 1,  -- = lane direction
+    g_bsn_monitor_sync_timeout => c_sdp_N_clk_sync_timeout_xsub
   )
   PORT MAP (
     mm_clk    => mm_clk,

applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd

@@ -120,7 +120,10 @@ BEGIN
     g_gain_w          => c_sdp_W_bf_weight,
     g_in_dat_w        => c_sdp_W_subband,
     g_out_dat_w       => c_gain_out_dat_w,
-    g_gains_file_name => g_gains_file_name
+    g_gains_file_name => g_gains_file_name,
+    -- extra input latency to ease timing.
+    g_pipeline_real_mult_input    => 2, 
+    g_pipeline_complex_mult_input => 2 
   )
   PORT MAP (
     -- System

applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd

@@ -114,6 +114,7 @@ PACKAGE sdp_pkg is
   CONSTANT c_sdp_wg_subband_freq_unit    : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft);  -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
   CONSTANT c_sdp_N_clk_per_sync          : NATURAL := c_sdp_f_adc_MHz*10**6;  -- Default 200M clock cycles per second
   CONSTANT c_sdp_N_clk_sync_timeout      : NATURAL := c_sdp_f_adc_MHz*10**6 + c_sdp_f_adc_MHz*10**5;  -- 10% margin.
+  CONSTANT c_sdp_N_clk_sync_timeout_xsub : NATURAL := 2**31 - 1;  -- 10.7 seconds = largest value for NATURAL.
   CONSTANT c_sdp_N_sync_jesd             : NATURAL := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN
   CONSTANT c_sdp_f_sub_Hz                : REAL := REAL(c_sdp_f_adc_MHz * 10**6) / REAL(c_sdp_N_fft);  -- = 195312.5
   CONSTANT c_sdp_N_int                   : NATURAL := c_sdp_f_adc_MHz * 10**6;  -- nof ADC sample periods per 1 s integration interval

applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd

@@ -114,7 +114,8 @@ ENTITY sdp_statistics_offload IS
     g_beamset_id               : NATURAL := 0;
     g_P_sq                     : NATURAL := c_sdp_P_sq;  -- number of available correlator cells,
     g_crosslets_direction      : NATURAL := 1; -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
-    g_reverse_word_order  : BOOLEAN := TRUE  -- default word order is MSB after LSB, we need to stream LSB after MSB.
+    g_reverse_word_order       : BOOLEAN := TRUE;  -- default word order is MSB after LSB, we need to stream LSB after MSB.
+    g_bsn_monitor_sync_timeout : NATURAL := c_sdp_N_clk_sync_timeout
   );
   PORT (
     -- Clocks and reset
@@ -575,7 +576,7 @@ BEGIN
   GENERIC MAP (
     g_nof_streams        => 1,  
     g_cross_clock_domain => TRUE,
-    g_sync_timeout       => c_sdp_N_clk_sync_timeout,
+    g_sync_timeout       => g_bsn_monitor_sync_timeout,
     g_bsn_w              => c_dp_stream_bsn_w,
     g_error_bi           => 0,
     g_cnt_sop_w          => c_word_w,

applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd

@@ -120,7 +120,10 @@ BEGIN
     g_gain_w          => c_sdp_W_sub_weight,
     g_in_dat_w        => c_sdp_W_subband,
     g_out_dat_w       => c_gain_out_dat_w,
-    g_gains_file_name => g_gains_file_name
+    g_gains_file_name => g_gains_file_name,
+    -- extra input latency to ease timing.
+    g_pipeline_real_mult_input    => 2, 
+    g_pipeline_complex_mult_input => 2 
   )
   PORT MAP (
     -- System

libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd

@@ -100,7 +100,7 @@ ARCHITECTURE str OF mms_dp_gain_serial_arr IS
   --   dat_w     : NATURAL;
   --   nof_dat   : NATURAL;    -- optional, nof dat words <= 2**adr_w
   --   init_sl   : STD_LOGIC;  -- optional, init all dat words to std_logic '0', '1' or 'X'
-  CONSTANT c_mm_ram : t_c_mem := (latency  => 2, -- set latency to 2 to ease timing
+  CONSTANT c_mm_ram : t_c_mem := (latency  => 1, 
                                   adr_w    => ceil_log2(g_nof_gains),
                                   dat_w    => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
                                   nof_dat  => g_nof_gains,

libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml

@@ -21,8 +21,8 @@ peripherals:
               bit_offset: 31
               mm_width: 1
               access_mode: RW
-          - - field_name: enable
-              field_description: "Enable JESD signal input i by setting bit i = 1, disable by clearing bit i = 0."
+          - - field_name: disable
+              field_description: "Disable JESD signal input i by setting bit i = 1, enable by clearing bit i = 0."
               address_offset: 0x0
               bit_offset: 0
               mm_width: 31