updated for using revisions (as in unb1_test). revision unb2_test_1GbE

to start with

boards/uniboard2/designs/unb2_test/doc/README

@@ -7,8 +7,12 @@ Start with the Oneclick Commands:
     python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2
     python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2
 
-Generate MMM for QSYS:
-    run_qsys unb2 unb2_test
+
+Generate MMM for QSYS (select one of these revisions):
+    run_qsys unb2 unb2_test_1GbE
+    run_qsys unb2 unb2_test_10GbE
+    run_qsys unb2 unb2_test_ddr
+    run_qsys unb2 unb2_test_all
 
 -> From here either continue to Modelsim (simulation) or Quartus (synthesis)
 
@@ -38,25 +42,33 @@ Modelsim instructions:
 
 Synthesis
 ---------
-Quartus instructions (for QSYS):
-    run_app unb2 unb2_test use=gen2
-    run_qcomp unb2 unb2_test
+Quartus instructions: (select one of these revisions):
+    run_qcomp unb2 unb2_test_10GbE
+    run_qcomp unb2 unb2_test_1GbE
+    run_qcomp unb2 unb2_test_ddr
+    run_qcomp unb2 unb2_test_all
+
 
 In case of needing the Quartus GUI for inspection:
     run_quartus unb2
 
 
 Convert .sof to .rbf:
-    run_rbf unb2 unb2_test
+    (select one of these revisions):
+    run_rbf unb2 unb2_test_10GbE
+    run_rbf unb2 unb2_test_1GbE
+    run_rbf unb2 unb2_test_ddr
+    run_rbf unb2 unb2_test_all
 
 
 Send to LCU capture5:
-    scp $RADIOHDL/build/quartus/unb2_test/unb2_test.rbf capture5:~/rbf/
+    # for example the unb2_test_10GbE revision:
+    scp $RADIOHDL/build/quartus/unb2_test_10GbE/unb2_test_10GbE.rbf capture5:~/rbf/
 
     # Now login on capture5 and use pythonscript to program flash:
     cd unb2_test/tb/python
 
     # for example use frontnode 0 on uniboard 0:
-    python tc_unb2_test.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb2_test.rbf
+    python tc_unb2_test.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb2_test_10GbE.rbf
     python tc_unb2_test.py --gn 0 --seq REMU,REGMAP,INFO,PPSH,SENSORS  # start design, read info-ppsh-sensors
 

boards/uniboard2/designs/unb2_test/hdllib.cfg

@@ -6,7 +6,6 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_arria10
 
 
-
 synth_files =
     src/vhdl/qsys_unb2_test_pkg.vhd
     src/vhdl/mmm_unb2_test.vhd
@@ -15,31 +14,3 @@ synth_files =
 test_bench_files = 
     tb/vhdl/tb_unb2_test.vhd
 
-synth_top_level_entity =
-
-quartus_copy_files =
-    quartus/qsys_unb2_test.qsys .
-    src/hex/counter_data_128_0.hex ../..
-    src/hex/counter_data_128_1.hex ../..
-    src/hex/counter_data_128_2.hex ../..
-    src/hex/counter_data_128_3.hex ../..
-    src/hex/counter_data_32_0.hex ../..
-    src/hex/counter_data_32_1.hex ../..
-    src/hex/counter_data_32_2.hex ../..
-    src/hex/counter_data_32_3.hex ../..
-    src/hex/counter_data_64_0.hex ../..
-    src/hex/counter_data_64_1.hex ../..
-    src/hex/counter_data_64_2.hex ../..
-    src/hex/counter_data_64_3.hex ../..
-
-quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
-
-quartus_tcl_files =
-    quartus/unb2_test_pins.tcl
-
-quartus_vhdl_files = 
-
-quartus_qip_files =
-    $HDL_BUILD_DIR/unb2/quartus/unb2_test/qsys_unb2_test/synthesis/qsys_unb2_test.qip
-

boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg

+hdl_lib_name = unb2_test_1GbE
+hdl_library_clause_name = unb2_test_1GbE_lib
+hdl_lib_uses_synth = common mm technology unb2_board unb2_test
+hdl_lib_uses_sim = 
+hdl_lib_excludes = ip_arria10_mac_10g
+
+hdl_lib_technology = ip_arria10
+
+synth_files =
+    unb2_test_1GbE.vhd
+
+test_bench_files = 
+#    tb_unb2_test_1GbE.vhd
+
+modelsim_copy_files =
+    ../../src/hex hex
+
+synth_top_level_entity =
+
+quartus_copy_files =
+    ../../quartus/qsys_unb2_test.qsys .
+    ../../src/hex hex
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+
+quartus_tcl_files =
+    quartus/unb2_test_1GbE_pins.tcl
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip

boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+#source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_all_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl

boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+
+ENTITY unb2_test_1GbE IS
+  GENERIC (
+    g_design_name      : STRING  := "unb2_test_1GbE";
+    g_design_note      : STRING  := "Test design with 1GbE";
+    g_sim              : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_unb_nr       : NATURAL := 0;
+    g_sim_node_nr      : NATURAL := 0;
+    g_stamp_date       : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time       : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
+    g_stamp_svn        : NATURAL := 0   -- SVN revision    -- set by QSF
+  );
+  PORT (
+    -- GENERAL
+    CLK          : IN    STD_LOGIC; -- System Clock
+    PPS          : IN    STD_LOGIC; -- System Sync
+    WDI          : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA         : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB         : INOUT STD_LOGIC; -- FPGA interconnect line
+
+    -- Others
+    VERSION      : IN    STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
+    ID           : IN    STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
+    TESTIO       : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+    
+    -- I2C Interface to Sensors
+    SENS_SC      : INOUT STD_LOGIC;
+    SENS_SD      : INOUT STD_LOGIC;
+  
+    -- 1GbE Control Interface
+    ETH_CLK      : IN    STD_LOGIC;
+    ETH_SGIN     : IN    STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+    ETH_SGOUT    : OUT   STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+
+    QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+  );
+END unb2_test_1GbE;
+
+
+ARCHITECTURE str OF unb2_test_1GbE IS
+
+BEGIN
+
+  u_revision : ENTITY unb2_test_lib.unb2_test
+  GENERIC MAP (
+    g_design_name => g_design_name,
+    g_design_note => g_design_note,
+    g_sim         => g_sim,
+    g_sim_unb_nr  => g_sim_unb_nr,
+    g_sim_node_nr => g_sim_node_nr,
+    g_stamp_date  => g_stamp_date,
+    g_stamp_time  => g_stamp_time,
+    g_stamp_svn   => g_stamp_svn
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => CLK,
+    PPS          => PPS,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => VERSION,
+    ID           => ID,
+    TESTIO       => TESTIO,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => SENS_SC,
+    SENS_SD      => SENS_SD,
+
+    -- 1GbE Control Interface
+    ETH_clk      => ETH_clk,
+    ETH_SGIN     => ETH_SGIN,
+    ETH_SGOUT    => ETH_SGOUT,
+
+    QSFP_LED     => QSFP_LED
+  );
+
+END str;

boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd

@@ -79,6 +79,7 @@ ENTITY mmm_unb2_test IS
     reg_ppsh_miso            : IN  t_mem_miso; 
                              
     -- eth1g
+    eth1g_mm_rst             : OUT STD_LOGIC;
     eth1g_tse_mosi           : OUT t_mem_mosi;  
     eth1g_tse_miso           : IN  t_mem_miso;  
     eth1g_reg_mosi           : OUT t_mem_mosi;  
@@ -283,7 +284,7 @@ BEGIN
       -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
       pio_wdi_external_connection_export        => pout_wdi,
 
-      avs_eth_0_reset_export                    => OPEN,
+      avs_eth_0_reset_export                    => eth1g_mm_rst,
       avs_eth_0_clk_export                      => OPEN,
       avs_eth_0_tse_address_export              => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
       avs_eth_0_tse_write_export                => eth1g_tse_mosi.wr,

boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd

@@ -46,12 +46,7 @@ ENTITY unb2_test IS
     g_stamp_date       : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time       : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
     g_stamp_svn        : NATURAL := 0;  -- SVN revision    -- set by QSF
-    g_factory_image    : BOOLEAN := FALSE;
-    g_nof_streams_1GbE : NATURAL := 0;
-    g_nof_streams_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
-    g_nof_streams_ring : NATURAL := c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
-    g_nof_streams_back0: NATURAL := c_unb2_board_tr_back.bus_w;
-    g_nof_streams_back1: NATURAL := c_unb2_board_tr_back.bus_w
+    g_factory_image    : BOOLEAN := FALSE
   );
   PORT (
     -- GENERAL
@@ -76,38 +71,38 @@ ENTITY unb2_test IS
     ETH_SGOUT    : OUT   STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
 
     -- Transceiver clocks
-    SA_CLK       : IN    STD_LOGIC; -- Clock 10GbE front (qsfp) and ring lines
-    SB_CLK       : IN    STD_LOGIC; -- Clock 10GbE back upper 24 lines
-    BCK_REF_CLK  : IN    STD_LOGIC; -- Clock 10GbE back lower 24 lines
+    SA_CLK       : IN    STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+    SB_CLK       : IN    STD_LOGIC := '0'; -- Clock 10GbE back upper 24 lines
+    BCK_REF_CLK  : IN    STD_LOGIC := '0'; -- Clock 10GbE back lower 24 lines
 
     -- back transceivers
-    BCK_RX       : IN    STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+    BCK_RX       : IN    STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
     BCK_TX       : OUT   STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
     BCK_SDA      : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
     BCK_SCL      : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
     BCK_ERR      : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
 
     -- ring transceivers
-    RING_0_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+    RING_0_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
     RING_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-    RING_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+    RING_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
     RING_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
     -- pmbus
     PMBUS_SC     : INOUT STD_LOGIC;
     PMBUS_SD     : INOUT STD_LOGIC;
-    PMBUS_ALERT  : IN    STD_LOGIC;
+    PMBUS_ALERT  : IN    STD_LOGIC := '0';
     -- front transceivers
-    QSFP_0_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_0_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
     QSFP_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-    QSFP_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
     QSFP_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-    QSFP_2_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_2_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
     QSFP_2_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-    QSFP_3_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_3_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
     QSFP_3_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-    QSFP_4_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_4_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
     QSFP_4_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-    QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
     QSFP_5_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
 
     QSFP_SDA     : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
@@ -125,8 +120,17 @@ ARCHITECTURE str OF unb2_test IS
   CONSTANT c_fw_version                 : t_unb2_board_fw_version := (1, 1);
 
   -- Revision controlled constants
-  CONSTANT c_use_1GbE                   : BOOLEAN := FALSE; --g_design_name = "unb2_test_1GbE";
-  CONSTANT c_use_10GbE                  : BOOLEAN := TRUE;  --g_design_name = "unb2_test_10GbE";
+  CONSTANT c_use_1GbE                   : BOOLEAN := g_design_name="unb2_test_1GbE"  OR g_design_name="unb2_test_10GbE" OR g_design_name="unb2_test_all";
+  CONSTANT c_use_10GbE                  : BOOLEAN := g_design_name="unb2_test_10GbE" OR g_design_name="unb2_test_all";
+  CONSTANT c_use_ddr                    : BOOLEAN := g_design_name="unb2_test_ddr"   OR g_design_name="unb2_test_all";
+
+  CONSTANT g_nof_streams_1GbE           : NATURAL := sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
+  CONSTANT g_nof_streams_qsfp           : NATURAL := sel_a_b(c_use_10GbE,c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,0);
+  CONSTANT g_nof_streams_ring           : NATURAL := sel_a_b(c_use_10GbE,c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,0);
+  CONSTANT g_nof_streams_back0          : NATURAL := sel_a_b(c_use_10GbE,c_unb2_board_tr_back.bus_w,0);
+  CONSTANT g_nof_streams_back1          : NATURAL := sel_a_b(c_use_10GbE,c_unb2_board_tr_back.bus_w,0);
+
+
   CONSTANT g_nof_streams                : NATURAL := g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back0 + g_nof_streams_back1 + g_nof_streams_1GbE;
   CONSTANT g_nof_qsfp_bus               : NATURAL := ceil_div(g_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w);
   CONSTANT g_nof_ring_bus               : NATURAL := ceil_div(g_nof_streams_ring,c_unb2_board_tr_ring.bus_w);
@@ -232,6 +236,7 @@ ARCHITECTURE str OF unb2_test IS
   SIGNAL reg_unb_sens_miso          : t_mem_miso;
 
   -- eth1g
+  SIGNAL eth1g_mm_rst               : STD_LOGIC;
   SIGNAL eth1g_tse_mosi             : t_mem_mosi;  -- ETH TSE MAC registers
   SIGNAL eth1g_tse_miso             : t_mem_miso;
   SIGNAL eth1g_reg_mosi             : t_mem_mosi;  -- ETH control and status registers
@@ -420,6 +425,7 @@ BEGIN
     reg_ppsh_miso            => reg_ppsh_miso,
     
     -- eth1g
+    eth1g_mm_rst             => eth1g_mm_rst,
     eth1g_tse_mosi           => eth1g_tse_mosi,
     eth1g_tse_miso           => eth1g_tse_miso,
     eth1g_reg_mosi           => eth1g_reg_mosi,
@@ -496,6 +502,7 @@ BEGIN
     reg_ppsh_miso            => reg_ppsh_miso, 
   
     -- eth1g
+    eth1g_mm_rst             => eth1g_mm_rst,
     eth1g_tse_mosi           => eth1g_tse_mosi,
     eth1g_tse_miso           => eth1g_tse_miso,
     eth1g_reg_mosi           => eth1g_reg_mosi,
@@ -559,6 +566,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- TX: Block generator
   -----------------------------------------------------------------------------
+  gen_bgdb_chain : IF c_use_1GbE=TRUE GENERATE
     u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
     GENERIC MAP (
       g_nof_streams        => g_nof_streams,
@@ -743,7 +751,7 @@ BEGIN
       in_sync           => diag_data_buf_snk_in_arr(0).sync,
       in_sosi_arr       => diag_data_buf_snk_in_arr
     );
-
+  END GENERATE;
 
 
   -----------------------------------------------------------------------------
@@ -876,9 +884,9 @@ BEGIN
       QSFP_RX    => i_QSFP_RX,
       QSFP_TX    => i_QSFP_TX,
 
-      QSFP_SDA   => QSFP_SDA,
-      QSFP_SCL   => QSFP_SCL,
-      QSFP_RST   => QSFP_RST,
+      --QSFP_SDA   => QSFP_SDA,
+      --QSFP_SCL   => QSFP_SCL,
+      --QSFP_RST   => QSFP_RST,
 
       QSFP_LED   => QSFP_LED
     );