Added eth_src_out to support further external analysis.

libraries/io/eth/src/vhdl/eth_statistics.vhd

@@ -60,6 +60,7 @@ ENTITY eth_statistics IS
   );
   PORT (
     eth_serial_in : IN  STD_LOGIC;
+    eth_src_out   : OUT t_dp_sosi;  -- Output received sosi
     tb_end        : OUT STD_LOGIC -- To be used to stop test-bench generated clocks
   );
 END eth_statistics;
@@ -148,4 +149,7 @@ BEGIN
     tb_end => i_tb_end
   );
 
+  -- Output the received decoded data, to support further external analysis
+  eth_src_out <= tech_tse_rx_src_out;
+
 END str;