Undo bg_bsn. Keep bsn_init.

libraries/base/diag/src/vhdl/diag_block_gen.vhd

@@ -96,8 +96,7 @@ entity diag_block_gen is
     ctrl_hold    : out t_diag_block_gen;  -- hold current active ctrl
     en_sync      : in  std_logic := '1';
     out_siso     : in  t_dp_siso := c_dp_siso_rdy;
-    out_sosi     : out t_dp_sosi;
-    out_bsn      : out std_logic_vector(c_diag_bg_bsn_init_w-1 downto 0)
+    out_sosi     : out t_dp_sosi
   );
   
 end diag_block_gen;
@@ -302,8 +301,6 @@ begin
     buf_addr <= TO_UVEC(r.mem_cnt, g_buf_addr_w);
     buf_rden <= r.rd_ena;
 
-    out_bsn <= rin.bsn_cnt when rising_edge(clk) and rin.sop = '1';
-
     ctrl_hold <= r.ctrl_hold;
  
 end rtl;

libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd

@@ -39,8 +39,7 @@ entity diag_block_gen_reg is
     dp_clk  : in  std_logic;
     mm_mosi : in  t_mem_mosi;                  -- Memory Mapped Slave in mm_clk domain
     mm_miso : out t_mem_miso       := c_mem_miso_rst;
-    bg_ctrl : out t_diag_block_gen := g_diag_block_gen_rst;
-    bg_bsn  : in  std_logic_vector(c_diag_bg_bsn_init_w-1 downto 0)
+    bg_ctrl : out t_diag_block_gen := g_diag_block_gen_rst
   ); 
 end diag_block_gen_reg;  
 
@@ -110,9 +109,9 @@ begin
           when 5 =>
             mm_miso.rddata(c_diag_bg_mem_high_adrs_w      -1 downto 0) <= mm_bg_ctrl.mem_high_adrs;
           when 6 =>
-            mm_miso.rddata(31 downto 0) <= bg_bsn(31 downto 0);
+            mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(31 downto 0);
           when 7 =>
-            mm_miso.rddata(31 downto 0) <= bg_bsn(63 downto 32);
+            mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
           when others => null;  -- not used MM addresses
         end case;
       end if; 

libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd

@@ -174,7 +174,6 @@ ARCHITECTURE rtl OF mms_diag_block_gen IS
   SIGNAL ram_bg_data_mosi_arr  : t_mem_mosi_arr(g_nof_streams   -1 DOWNTO 0);
   SIGNAL ram_bg_data_miso_arr  : t_mem_miso_arr(g_nof_streams   -1 DOWNTO 0); 
   SIGNAL bg_ctrl               : t_diag_block_gen;
-  SIGNAL bg_bsn                : STD_LOGIC_VECTOR(c_diag_bg_bsn_init_w-1 downto 0);
 
   SIGNAL mux_ctrl              : NATURAL RANGE 0 TO c_mux_nof_input-1;
   SIGNAL mux_snk_out_2arr_2    : t_dp_siso_2arr_2(g_nof_streams-1 DOWNTO 0);  -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
@@ -217,8 +216,7 @@ BEGIN
       dp_clk  => dp_clk,
       mm_mosi => reg_bg_ctrl_mosi,
       mm_miso => reg_bg_ctrl_miso,
-      bg_ctrl => bg_ctrl,
-      bg_bsn  => bg_bsn
+      bg_ctrl => bg_ctrl
     );
     
     -- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
@@ -290,8 +288,7 @@ BEGIN
         ctrl_hold  => bg_ctrl_hold_arr(I),  -- active BG control can differ in time per stream
         en_sync    => en_sync,
         out_siso   => bg_src_in_arr(I),
-        out_sosi   => bg_src_out_arr(I),
-        out_bsn    => bg_bsn
+        out_sosi   => bg_src_out_arr(I)
       );
     END GENERATE;
   END GENERATE;

libraries/io/eth/tb/vhdl/tb_eth_tester.vhd

@@ -161,8 +161,6 @@ ARCHITECTURE tb OF tb_eth_tester IS
   -- Use same bg_ctrl for all others streams, this provides sufficient test coverage
   SIGNAL bg_ctrl_arr         : t_diag_block_gen_integer_arr(g_nof_streams-1 DOWNTO 0);
 
-  SIGNAL bg_bsn              : STD_LOGIC_VECTOR(c_diag_bg_bsn_init_w-1 downto 0);
-
   SIGNAL tx_fifo_rd_emp_arr  : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
 
   -- ETH UDP data path interface
@@ -362,22 +360,6 @@ BEGIN
     END IF;
     ASSERT c_bg_nof_bps_total < 10.0**9 REPORT "Tx flow control will keep ETH bitrate < 1Gbps." SEVERITY NOTE;
 
-    -------------------------------------------------------------------------
-    -- Manually verify: BG nof blocks and BSN
-    -------------------------------------------------------------------------
-    FOR I IN g_nof_streams-1 DOWNTO 0 LOOP
-      v_offset := I * c_diag_bg_reg_adr_span;
-
-      -- Read current BSN from BG
-      proc_mem_mm_bus_rd(v_offset + 6, mm_clk, reg_bg_ctrl_cipo, reg_bg_ctrl_copi);  -- low part
-      proc_mem_mm_bus_rd_latency(1, mm_clk);
-      bg_bsn(31 DOWNTO 0) <= reg_bg_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0);
-      proc_mem_mm_bus_rd(v_offset + 7, mm_clk, reg_bg_ctrl_cipo, reg_bg_ctrl_copi);  -- high part
-      proc_mem_mm_bus_rd_latency(1, mm_clk);
-      bg_bsn(63 DOWNTO 32) <= reg_bg_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0);
-      proc_common_wait_some_cycles(mm_clk, 1);
-    END LOOP;
-
     -------------------------------------------------------------------------
     -- Verification: Total counts
     -------------------------------------------------------------------------