adapt changed io_ddr

boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd

@@ -103,14 +103,14 @@ ENTITY unb1_test IS
     BN_BI_3_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
 
     -- SO-DIMM Memory Bank I
-    MB_I_IN       : IN    t_tech_ddr_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0) := (OTHERS=>c_tech_ddr_phy_in_rst);
-    MB_I_IO       : INOUT t_tech_ddr_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);-- := (OTHERS=>c_tech_ddr_phy_io_rst);
-    MB_I_OU       : OUT   t_tech_ddr_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0)
+    MB_I_IN       : IN    t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
+    MB_I_IO       : INOUT t_tech_ddr3_phy_io;
+    MB_I_OU       : OUT   t_tech_ddr3_phy_ou
 
     -- SO-DIMM Memory Bank II                                                                    
---    MB_II_IN      : IN    t_tech_ddr_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0);
---    MB_II_IO      : INOUT t_tech_ddr_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0);
---    MB_II_OU      : OUT   t_tech_ddr_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0)
+    -- MB_II_IN      : IN    t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
+    -- MB_II_IO      : INOUT t_tech_ddr3_phy_io;
+    -- MB_II_OU      : OUT   t_tech_ddr3_phy_ou
   );
 END unb1_test;
 
@@ -988,11 +988,10 @@ BEGIN
   gen_MB_I : IF g_use_MB_I = 1 GENERATE
     u_mms_ddr3_i: ENTITY io_ddr_lib.io_ddr
     GENERIC MAP (
-      g_technology           => g_technology,
-      g_tech_ddr             => c_ddr_master,
-      g_use_ddr_memory_model => g_sim,
-      g_wr_data_w            => c_st_dat_w,
-      g_rd_data_w            => c_st_dat_w
+      g_technology       => g_technology,
+      g_tech_ddr         => c_ddr_master,
+      g_wr_data_w        => c_st_dat_w,
+      g_rd_data_w        => c_st_dat_w
     )
     PORT MAP (
       mm_clk             => mm_clk,
@@ -1031,9 +1030,9 @@ BEGIN
       term_ctrl_out      => OPEN,
       term_ctrl_in       => OPEN,
 
-      phy_in             => MB_I_IN(0),
-      phy_io             => MB_I_IO(0),
-      phy_ou             => MB_I_OU(0)
+      phy3_in            => MB_I_IN,
+      phy3_io            => MB_I_IO,
+      phy3_ou            => MB_I_OU
     );
   END GENERATE;
 
@@ -1046,17 +1045,22 @@ BEGIN
 --    u_mms_ddr3_ii: ENTITY io_ddr_lib.io_ddr
 --    GENERIC MAP (
 --      g_technology       => g_technology,
---      g_tech_ddr         => c_ddr_slave,
---      g_sim              => g_sim,
+--      g_tech_ddr         => c_ddr_master,
 --      g_wr_data_w        => c_st_dat_w,
 --      g_rd_data_w        => c_st_dat_w
 --    )
 --    PORT MAP (
+--      mm_clk             => mm_clk,
+--      mm_rst             => mm_rst,
+--
+--      reg_io_ddr_mosi    => reg_io_ddr_mosi2,
+--      reg_io_ddr_miso    => reg_io_ddr_miso2,
+--
 --      ctlr_ref_clk       => dp_clk,
 --      ctlr_ref_rst       => dp_rst,
 --
 --      ctlr_clk_out       => ddr_ctlr_clk(1),
---      ctlr_clk_in        => ddr_ctlr_clk(1), -- connect ctlr_clk_out to ctlr_clk_in to avoid potential delta-cycle differences between the same clock
+--      ctlr_clk_in        => ddr_ctlr_clk(1),
 --
 --      ctlr_rst_out       => ddr_ctlr_rst(1),
 --      ctlr_rst_in        => ddr_ctlr_rst(1),
@@ -1079,9 +1083,12 @@ BEGIN
 --      rd_sosi            => from_mem_sosi2,
 --      rd_siso            => from_mem_siso2,
 --
---      phy_in             => MB_II_IN(0),
---      phy_io             => MB_II_IO(0),
---      phy_ou             => MB_II_OU(0)
+--      term_ctrl_out      => OPEN,
+--      term_ctrl_in       => OPEN,
+--
+--      phy3_in            => MB_I_IN,
+--      phy3_io            => MB_I_IO,
+--      phy3_ou            => MB_I_OU
 --    );
 --  END GENERATE;