Renamed g_clk_*_period into g_ref_clk_*_period. Added tr_ref_rst_156 IN port for XAUI.

libraries/technology/eth_10g/tb_tech_eth_10g.vhd

@@ -47,8 +47,9 @@ ENTITY tb_tech_eth_10g IS
   -- Test bench control parameters
   GENERIC (
     g_technology              : NATURAL := c_tech_select_default;
-    g_clk_644_period          : TIME := tech_pll_clk_644_period;
-    g_clk_156_period          : TIME := 6.4 ns;
+    g_sim_level               : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
+    g_ref_clk_644_period      : TIME := tech_pll_clk_644_period;  -- for 10GBASE-R
+    g_ref_clk_156_period      : TIME := 6.4 ns;                   -- for XAUI
     g_data_type               : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
     g_verify_link_recovery    : BOOLEAN := TRUE;
     g_link_status_check       : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
@@ -57,10 +58,10 @@ ENTITY tb_tech_eth_10g IS
   PORT (
     -- PHY 10gbase_r
     serial_tx_out   : OUT STD_LOGIC;                                       -- 1 lane
-    serial_rx_in    : IN  STD_LOGIC;
+    serial_rx_in    : IN  STD_LOGIC := 'X';
     -- PHY XAUI
     xaui_tx_out     : OUT STD_LOGIC_VECTOR(c_nof_xaui_lanes-1 DOWNTO 0);   -- 4 lanes
-    xaui_rx_in      : IN  STD_LOGIC_VECTOR(c_nof_xaui_lanes-1 DOWNTO 0)
+    xaui_rx_in      : IN  STD_LOGIC_VECTOR(c_nof_xaui_lanes-1 DOWNTO 0) := (OTHERS=>'X')
   );
 END tb_tech_eth_10g;
 
@@ -108,6 +109,7 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
 
   -- . XAUI clocks
   SIGNAL tr_ref_clk_156    : STD_LOGIC := '1';
+  SIGNAL tr_ref_rst_156    : STD_LOGIC := '1';
   SIGNAL tx_rst_arr        : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL rx_clk_arr_out    : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL rx_rst_arr        : STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -115,6 +117,7 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
   -- . Test bench top level clocks 
   SIGNAL tb_ref_clk_644    : STD_LOGIC;
   SIGNAL tb_ref_clk_156    : STD_LOGIC;
+  SIGNAL tb_ref_rst_156    : STD_LOGIC;
   SIGNAL tb_clk_312        : STD_LOGIC;
   SIGNAL tb_clk_156        : STD_LOGIC;
   SIGNAL tb_rst_156        : STD_LOGIC;
@@ -216,9 +219,11 @@ BEGIN
   rx_siso_arr(0) <= rx_siso;
   rx_sosi        <= rx_sosi_arr(0);
   
-  tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER g_clk_644_period/2;
-  tr_ref_clk_156 <= NOT tr_ref_clk_156 AFTER g_clk_156_period/2;
+  tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER g_ref_clk_644_period/2;
+  tr_ref_clk_156 <= NOT tr_ref_clk_156 AFTER g_ref_clk_156_period/2;
 
+  tr_ref_rst_156 <= '0' AFTER g_ref_clk_156_period*5;
+  
   pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
   GENERIC MAP (
     g_technology => g_technology
@@ -234,6 +239,7 @@ BEGIN
   -- Connect the clocks from test bench top level (down such that they have their rising_edge() aligned without any delta-delay)
   gen_tb_clocks_xaui : IF g_technology=c_tech_stratixiv GENERATE
     tb_ref_clk_156 <= tr_ref_clk_156;
+    tb_ref_rst_156 <= tr_ref_rst_156;
     tb_tx_clk      <= tr_ref_clk_156;
     tb_rx_clk      <= rx_clk_arr_out(0);
     tb_tx_rst      <= tx_rst_arr(0);
@@ -258,7 +264,8 @@ BEGIN
     dut : ENTITY work.tech_eth_10g
     GENERIC MAP (
       g_technology          => g_technology,
-      g_sim                 => FALSE,
+      g_sim                 => TRUE,
+      g_sim_level           => g_sim_level,
       g_nof_channels        => 1,
       g_link_status_check   => g_link_status_check,
       --g_pre_header_padding  => FALSE
@@ -268,6 +275,7 @@ BEGIN
       -- Transceiver PLL reference clock
       tr_ref_clk_644   => tb_ref_clk_644,
       tr_ref_clk_156   => tb_ref_clk_156,
+      tr_ref_rst_156   => tb_ref_rst_156,
       
       -- MM
       mm_clk           => mm_clk,