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Commit 7c61e048 authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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Test bench for atrs SC3 output stage

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applications/arts/designs/arts_unb2b_sc3/hdllib.cfg
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...@@ -42,6 +42,7 @@ synth_files = ...@@ -42,6 +42,7 @@ synth_files =
test_bench_files = test_bench_files =
# tb/vhdl/tb_arts_unb2b_sc3.vhd # tb/vhdl/tb_arts_unb2b_sc3.vhd
tb/vhdl/tb_arts_unb2b_sc3_processing.vhd tb/vhdl/tb_arts_unb2b_sc3_processing.vhd
tb/vhdl/tb_arts_unb2b_sc3_output.vhd
[modelsim_project_file] [modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
......
applications/arts/designs/arts_unb2b_sc3/tb/vhdl/tb_arts_unb2b_sc3_output.vhd 0 → 100644
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View file @ 7c61e048
-------------------------------------------------------------------------------
--
-- Copyright (C) 2016
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose:
-- Simulate the output stage of the ARTS SC3 design separately for speed
-- Description:
-- Derived from the SC4 output testbench, but with 9 TABs and 120 beamlets (6 bit mode)
-- Testbench generates stimuli to represent the four frequency channel inputs from the processing stage
-- Usage (ModelSim) :
-- . lp arts_unb2b_sc3
-- . mk compile (all)
-- . (double click tb_arts_unb2a_sc3_output)
-- . do wave_*.do (optional ready made wave configuration)
-- . run -a
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, dp_lib, diag_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE unb2b_board_lib.unb2_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_arts_unb2b_sc3_output IS
END tb_arts_unb2b_sc3_output;
ARCHITECTURE tb OF tb_arts_unb2b_sc3_output IS
----------------------------------------------------------------------------
-- Clocks & reset, general setup
----------------------------------------------------------------------------
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_nof_cbsets : NATURAL := 1;
CONSTANT c_nof_tabs : NATURAL := 9;
CONSTANT c_nof_bytes_per_iquv_packet : NATURAL := 8000;
CONSTANT c_nof_bytes_per_i_packet : NATURAL := 6250;
CONSTANT c_nof_beamlets : NATURAL := 120; -- 88 for eight bit mode
CONSTANT c_nof_seq : NATURAL := 2; --4; -- 2 for halfrate
CONSTANT c_nof_timesamples : NATURAL := 6250*c_nof_seq;
CONSTANT c_nof_subbands : NATURAL := 24;
CONSTANT c_nof_channels : NATURAL := 4;
CONSTANT c_channel_int : NATURAL := 8;
CONSTANT c_stokes_int : NATURAL := 2;
CONSTANT c_iquv_data_w_out : NATURAL := 8; -- 8b Stokes parameters
CONSTANT c_dp_clk_period : TIME := 5 ns;
CONSTANT c_mm_clk_period : TIME := 20 ns;
SIGNAL valid_cycle_count : NATURAL;
SIGNAL dp_clk : STD_LOGIC := '0';
SIGNAL dp_rst : STD_LOGIC := '1';
SIGNAL dp_pps : STD_LOGIC := '0';
SIGNAL mm_clk : STD_LOGIC := '0';
SIGNAL mm_rst : STD_LOGIC := '1';
-------------------------------------------------------------------------------
-- arts_unb2b_sc3_output
-------------------------------------------------------------------------------
SIGNAL arts_unb2b_sc3_processing_src_out_2arr_9 : t_dp_sosi_2arr_9(c_nof_cbsets-1 DOWNTO 0) := (OTHERS => (OTHERS => c_dp_sosi_rst)); -- 8 CB sets * 9 TABs
SIGNAL arts_unb2b_sc3_stimulus : t_dp_sosi;
SIGNAL arts_unb2b_sc3_output_src_out_arr : t_dp_sosi_arr(c_nof_cbsets-1 DOWNTO 0); --8 CB sets, 1 CB set per output 10GbE fiber
SIGNAL arts_unb2b_sc3_output_src_in_arr : t_dp_siso_arr(c_nof_cbsets-1 DOWNTO 0);
SIGNAL tab_src_in : t_dp_siso;
SIGNAL reg_dp_offload_tx_iab_i_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_xonoff_iab_i_mosi : t_mem_mosi;
SIGNAL general_bsn : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL general_bsn_arr : t_slv_64_arr(c_nof_cbsets-1 DOWNTO 0);
----------------------------------------------------------------------------
-- dp_statistics
----------------------------------------------------------------------------
CONSTANT c_dp_statistics_check_nof_packets : NATURAL := 8-1; --FIXME Why is the 1st burst only 3 packets (hence -1)
CONSTANT c_dp_statistics_packet_size : NATURAL := c_nof_bytes_per_i_packet/4+24; --24 word header
CONSTANT c_dp_statistics_data_rate : NATURAL := 62; -- We expect 70MBps in 8b mode (88 beamlets). Account for 'missing' packet (7/8 data rate)
SIGNAL tb_end : STD_LOGIC := '0';
BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
dp_rst <= '0' AFTER 1 us;
mm_rst <= '0' AFTER 1 us;
dp_clk <= NOT dp_clk OR tb_end AFTER c_dp_clk_period/2;
mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
p_pps : PROCESS
BEGIN
WAIT UNTIL dp_rst='0';
WAIT FOR 1 us;
WAIT UNTIL rising_edge(dp_clk);
dp_pps <= '1';
WAIT UNTIL rising_edge(dp_clk);
dp_pps <= '0';
END PROCESS;
p_stimuli : PROCESS
VARIABLE v_bsn : NATURAL := 43;
BEGIN
WAIT UNTIL dp_rst='0';
WAIT FOR 10 us; -- start with the default gain setting of 1
arts_unb2b_sc3_stimulus.valid <= '0';
arts_unb2b_sc3_stimulus.data <= (others => '0');
valid_cycle_count <= 0;
WAIT UNTIL rising_edge(dp_clk);
WHILE TRUE LOOP
general_bsn <= TO_UVEC(v_bsn, 64);
v_bsn := v_bsn + 800000;
FOR i IN 0 TO c_nof_beamlets LOOP -- 5 cb x 24 sb in 6b mode
FOR j IN 0 TO c_nof_timesamples-1 LOOP -- time seqence of 4 x 6250 byte packets
FOR k IN 0 TO c_nof_channels-1 LOOP -- 4 channels
FOR l IN 0 TO c_channel_int-1 LOOP -- 8 clocks per integration
FOR m IN 0 TO c_stokes_int-1 LOOP -- Data rate is reduced by half (X,Y pol -> Stokes value)
IF l = 7 AND m = 1 THEN
arts_unb2b_sc3_stimulus.valid <= '1';
arts_unb2b_sc3_stimulus.data(7 downto 0) <= TO_UVEC(k+1,8);
valid_cycle_count <= valid_cycle_count+1;
ELSE
arts_unb2b_sc3_stimulus.valid <= '0';
arts_unb2b_sc3_stimulus.data(7 downto 0) <= (others => '0');
-- Our valid ratio is c_nof_beamlets/128
IF valid_cycle_count rem c_nof_beamlets = 0 THEN
valid_cycle_count <= 0;
WAIT FOR (128-c_nof_beamlets)*c_dp_clk_period; --Introduce the correct gap
END IF;
END IF;
WAIT UNTIL rising_edge(dp_clk); -- End of this (valid or invalid) clk cycle.
END LOOP;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
WAIT FOR 10 us; -- run on for a bit
END PROCESS;
p_mmctrl : PROCESS
BEGIN
WAIT UNTIL mm_rst='0';
WAIT FOR 1 us;
WAIT UNTIL rising_edge(mm_clk);
reg_dp_xonoff_iab_i_mosi.address <= TO_UVEC(0,c_mem_address_w);
reg_dp_xonoff_iab_i_mosi.wr <= '1';
reg_dp_xonoff_iab_i_mosi.wrdata <= TO_UVEC(1,c_mem_data_w);
WAIT UNTIL rising_edge(dp_clk);
reg_dp_xonoff_iab_i_mosi.wr <= '0';
END PROCESS;
p_sink_ready : PROCESS
VARIABLE sink_ready_count : NATURAL := 0;
BEGIN
WAIT UNTIL dp_rst='0';
tab_src_in.ready <= '0';
tab_src_in.xon <= '0';
WAIT FOR 1 us;
WAIT UNTIL rising_edge(dp_clk);
tab_src_in.ready <= '1';
tab_src_in.xon <= '1';
WHILE TRUE LOOP
IF sink_ready_count = 3 THEN
sink_ready_count := 0;
tab_src_in.ready <= '0';
ELSE
sink_ready_count := sink_ready_count + 1;
tab_src_in.ready <= '1';
END IF;
WAIT UNTIL rising_edge(dp_clk);
END LOOP;
END PROCESS;
p_assign_inputs : PROCESS (arts_unb2b_sc3_stimulus)
BEGIN
FOR i IN 0 TO c_nof_cbsets-1 LOOP
arts_unb2b_sc3_output_src_in_arr(0) <= tab_src_in;
IF i = 0 THEN
arts_unb2b_sc3_processing_src_out_2arr_9(i) <= (others => arts_unb2b_sc3_stimulus);
ELSE
arts_unb2b_sc3_processing_src_out_2arr_9(i) <= (others => c_dp_sosi_rst);
END IF;
END LOOP;
END PROCESS;
gen_general_bsn : FOR i IN 0 TO c_nof_cbsets-1 GENERATE
general_bsn_arr(i) <= general_bsn;
END GENERATE;
------------------------------------------------------------------------------
-- The DUT - ARTS SC3 output module
------------------------------------------------------------------------------
u_arts_unb2b_sc3_output : ENTITY work.arts_unb2b_sc3_output
GENERIC MAP (
g_sim => c_sim,
g_nof_cbsets => c_nof_cbsets,
g_nof_beamlets => c_nof_beamlets,
g_nof_subbands_per_cb => c_nof_subbands,
g_nof_channels => c_nof_channels,
g_nof_tabs => c_nof_tabs,
g_iquv_data_w_out => c_iquv_data_w_out
)
PORT MAP (
dp_clk => dp_clk,
dp_rst => dp_rst,
mm_clk => mm_clk,
mm_rst => mm_rst,
snk_in_2arr_9 => arts_unb2b_sc3_processing_src_out_2arr_9,
general_bsn_arr => general_bsn_arr,
src_out_arr => arts_unb2b_sc3_output_src_out_arr,
src_in_arr => arts_unb2b_sc3_output_src_in_arr,
reg_dp_offload_tx_tab_iquv_hdr_dat_mosi => c_mem_mosi_rst,
reg_dp_offload_tx_tab_iquv_hdr_dat_miso => OPEN,
reg_dp_xonoff_tab_iquv_mosi => c_mem_mosi_rst,
reg_dp_xonoff_tab_iquv_miso => OPEN,
reg_dp_offload_tx_tab_i_hdr_dat_mosi => c_mem_mosi_rst,
reg_dp_offload_tx_tab_i_hdr_dat_miso => OPEN,
reg_tab_dest_ip_mosi => c_mem_mosi_rst,
reg_tab_dest_ip_miso => OPEN,
reg_tab_dest_mac_mosi => c_mem_mosi_rst,
reg_tab_dest_mac_miso => OPEN,
reg_dp_xonoff_tab_i_mosi => c_mem_mosi_rst,
reg_dp_xonoff_tab_i_miso => OPEN,
ID => "00000000"
);
------------------------------------------------------------------------------
-- Verify proper DUT output using DP packet statistics
------------------------------------------------------------------------------
u_dp_statistics : ENTITY dp_lib.dp_statistics
GENERIC MAP (
g_runtime_nof_packets => c_dp_statistics_check_nof_packets,
g_runtime_timeout => 20000000 ns,
g_check_nof_valid => TRUE,
g_check_nof_valid_ref => c_dp_statistics_check_nof_packets*c_dp_statistics_packet_size,
g_check_data_rate_mbps => TRUE,
g_check_data_rate_mbps_ref => c_dp_statistics_data_rate
)
PORT MAP (
dp_clk => dp_clk,
dp_rst => dp_rst,
snk_in => arts_unb2b_sc3_output_src_out_arr(0),
tb_end => tb_end
--tb_end => open
);
END tb;
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