Renamed g_pipeline_miso_rd into g_pipeline_miso_rdval.

libraries/base/mm/src/vhdl/mm_bus.vhd

@@ -80,7 +80,7 @@
 --     pulse would yield a different pipelining of the address for write and
 --     for read, which is akward. Therefore assume that both mosi write and
 --     mosi read have the same pipelining.
---   . g_pipeline_miso_rd
+--   . g_pipeline_miso_rdval
 --     Pipelining the miso read data increases the read latency.
 --   . g_pipeline_miso_wait
 --     Pipelining the miso waitrequest increases the write and read latency
@@ -88,7 +88,7 @@
 --   The total write latency from master to slave is c_pipeline_mosi.
 --   The total read latency from master via slave back to master is
 --   c_pipeline_mosi + g_rd_latency_arr of the selected slave + 
---   c_pipeline_miso_rd. 
+--   c_pipeline_miso_rdval. 
 --     
 -- Usage:
 --   The ascii drawing shows how this mm_bus can be used in combination
@@ -136,6 +136,13 @@
 -- * No support yet for g_pipeline_miso_wait = TRUE. This requires an MM
 --   latency adapter for the mosi dependent on the miso.waitrequest.
 --
+-- Todo:
+-- * The mm_bus assumes that the MM slave will pull miso.waitrequest low.
+--   To avoid that the MM bus accesss will stall, a MM slave port that uses
+--   mosi flow control should also support an waitrequest timeout mechanism.
+--   The master can then be informed about the failing mosi access using
+--   the miso.response field of the Avalon bus.
+--
 -- Remarks:
 -- . The mm_bus resembles common_mem_mux, but the difference is that
 --   with common_mem_mux all slaves have the same address range and are
@@ -156,13 +163,13 @@ USE common_lib.common_mem_pkg.ALL;
 
 ENTITY mm_bus IS
   GENERIC (
-    g_nof_slaves         : POSITIVE;           -- Number of MM slave interfaces on the bus
-    g_base_arr           : t_nat_natural_arr;  -- Address base per slave
-    g_width_arr          : t_nat_natural_arr;  -- Address width per slave
-    g_rd_latency_arr     : t_nat_natural_arr;  -- Read latency per slave
-    g_pipeline_mosi      : BOOLEAN := FALSE;   -- Pipeline MM access (wr, rd)
-    g_pipeline_miso_rd   : BOOLEAN := FALSE;   -- Pipeline MM read (rdval)
-    g_pipeline_miso_wait : BOOLEAN := FALSE    -- Pipeline MM access flow control (waitrequest)
+    g_nof_slaves          : POSITIVE;           -- Number of MM slave interfaces on the bus
+    g_base_arr            : t_nat_natural_arr;  -- Address base per slave
+    g_width_arr           : t_nat_natural_arr;  -- Address width per slave
+    g_rd_latency_arr      : t_nat_natural_arr;  -- Read latency per slave
+    g_pipeline_mosi       : BOOLEAN := FALSE;   -- Pipeline MM access (wr, rd)
+    g_pipeline_miso_rdval : BOOLEAN := FALSE;   -- Pipeline MM read (rdval)
+    g_pipeline_miso_wait  : BOOLEAN := FALSE    -- Pipeline MM access flow control (waitrequest)
   );
   PORT (
     mm_clk         : IN  STD_LOGIC := '0';
@@ -195,11 +202,11 @@ ARCHITECTURE rtl OF mm_bus IS
     RETURN ceil_log2(v_mm_bus_addr_max);
   END;
   
-  CONSTANT c_mm_bus_addr_w      : NATURAL := func_derive_mm_bus_addr_w(g_base_arr, g_width_arr);
-  CONSTANT c_pipeline_mosi      : NATURAL := sel_a_b(g_pipeline_mosi, 1, 0);
-  CONSTANT c_pipeline_miso_rd   : NATURAL := sel_a_b(g_pipeline_miso_rd, 1, 0);
-  CONSTANT c_pipeline_miso_wait : NATURAL := sel_a_b(g_pipeline_miso_wait, 1, 0);
-  CONSTANT c_index_latency_max  : NATURAL := c_pipeline_mosi + largest(g_rd_latency_arr);
+  CONSTANT c_mm_bus_addr_w       : NATURAL := func_derive_mm_bus_addr_w(g_base_arr, g_width_arr);
+  CONSTANT c_pipeline_mosi       : NATURAL := sel_a_b(g_pipeline_mosi, 1, 0);
+  CONSTANT c_pipeline_miso_rdval : NATURAL := sel_a_b(g_pipeline_miso_rdval, 1, 0);
+  CONSTANT c_pipeline_miso_wait  : NATURAL := sel_a_b(g_pipeline_miso_wait, 1, 0);
+  CONSTANT c_index_latency_max   : NATURAL := c_pipeline_mosi + largest(g_rd_latency_arr);
 
   SIGNAL index_pipeline      : t_nat_natural_arr(0 TO c_index_latency_max) := (OTHERS=>0);
   SIGNAL slave_mosi_arr_comb : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
@@ -215,7 +222,6 @@ BEGIN
   END GENERATE;
     
   gen_multiple : IF g_nof_slaves>1 GENERATE 
-
     -- Detect which slave in the array is addressed
     p_index : PROCESS(master_mosi)
       VARIABLE v_base : NATURAL;
@@ -246,7 +252,8 @@ BEGIN
         END IF;
       END LOOP;
     END PROCESS;
-    
+
+    -- FIX ME: g_pipeline_mosi in combination with g_pipeline_miso_wait 
     slave_mosi_arr_reg <= slave_mosi_arr_comb WHEN rising_edge(mm_clk);
     
     slave_mosi_arr <= slave_mosi_arr_comb WHEN g_pipeline_mosi = FALSE ELSE slave_mosi_arr_reg;
@@ -275,7 +282,7 @@ BEGIN
     p_master_miso : PROCESS(master_miso_comb, master_miso_reg)
     BEGIN
       master_miso <= master_miso_comb;  -- default no miso pipelining
-      IF g_pipeline_miso_rd THEN
+      IF g_pipeline_miso_rdval THEN
         master_miso.rddata <= master_miso_reg.rddata;
         master_miso.rdval  <= master_miso_reg.rdval;
       END IF;
@@ -283,6 +290,7 @@ BEGIN
         master_miso.waitrequest <= master_miso_reg.waitrequest;
       END IF;
     END PROCESS;
+    
   END GENERATE; 
   
 END rtl;