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libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.dp_stream_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE work.tb_dp_pkg.ALL;
+
+-- Purpose: Test bench to check reinterleave function on DP level
+-- Usage:
+--   > as 6
+--   > run 2us
+-- Remark: 
+--   This TB is only used to visually inspect the wave window to see
+--   if all functions well on DP level. The actual reinterleaving itself
+--   is verified more thoroughly in tb_common_reinterleave.
+
+ENTITY tb_dp_reinterleave IS
+  GENERIC (
+    g_dat_w          : NATURAL := 16;
+    g_nof_in         : NATURAL := 4;  
+    g_deint_block_size  : NATURAL := 2;
+    g_nof_out        : NATURAL := 4;
+    g_inter_block_size : NATURAL := 2;
+    g_use_complex    : BOOLEAN := TRUE;
+    g_align_out  : BOOLEAN := TRUE
+ );
+END;
+
+ARCHITECTURE rtl OF tb_dp_reinterleave IS
+
+  TYPE t_dat_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+  TYPE t_val_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC;
+
+  -----------------------------------------------------------------------------
+  -- Standard TB clocking, RST and control
+  -----------------------------------------------------------------------------
+  CONSTANT c_clk_period : TIME := 10 ns;
+
+  SIGNAL clk            : STD_LOGIC := '1';
+  SIGNAL rst            : STD_LOGIC;
+  SIGNAL tb_end         : STD_LOGIC := '0';
+
+  SIGNAL cnt_ena        : STD_LOGIC;
+
+  -----------------------------------------------------------------------------
+  --I/O streams
+  -----------------------------------------------------------------------------
+  CONSTANT c_input_val   : NATURAL := 192;
+  CONSTANT c_input_inval : NATURAL := 64;
+
+  SIGNAL snk_in_arr  : t_dp_sosi_arr(g_nof_in-1 DOWNTO 0);
+  SIGNAL snk_out_arr : t_dp_siso_arr(g_nof_in-1 DOWNTO 0);
+
+  SIGNAL src_out_arr : t_dp_sosi_arr(g_nof_out-1 DOWNTO 0);
+  
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- Standard TB clocking, RST and control
+  -----------------------------------------------------------------------------
+  clk    <= NOT clk OR tb_end AFTER c_clk_period/2;
+  rst    <= '1', '0' AFTER 3*c_clk_period;
+
+  -----------------------------------------------------------------------------
+  -- Generate g_nof_in test data streams with counter data
+  -----------------------------------------------------------------------------
+  cnt_ena <= '0', '1' AFTER 20*c_clk_period;
+
+  gen_cnt_dat : FOR i IN 0 TO g_nof_in-1 GENERATE 
+    p_stimuli : PROCESS
+      VARIABLE v_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+    BEGIN
+      WHILE TRUE LOOP
+        WAIT UNTIL rising_edge(clk);
+        proc_dp_gen_block_data(1, sel_a_b(g_use_complex, FALSE, TRUE), g_dat_w, g_dat_w, 0, 0, 0, c_input_val, 0, 0, '1', v_bsn, clk, cnt_ena, snk_out_arr(i), snk_in_arr(i));
+        proc_common_wait_some_cycles(clk, c_input_inval);
+        v_bsn := INCR_UVEC(v_bsn, 1);
+      END LOOP;
+     END PROCESS;
+
+    -----------------------------------------------------------------------------
+    -- The I/O of common_reinterleave and its lower level components operate 
+    -- on the same data width share the same clock, so if g_nof_in>g_nof_out, 
+    -- lower the effective input data rate accordingly by introducing gaps.
+    -----------------------------------------------------------------------------
+    p_cnt_dat_gaps : PROCESS
+    BEGIN
+      snk_out_arr(i).xon <= '1';
+      snk_out_arr(i).ready  <= '0';
+      WAIT FOR c_clk_period * (ceil_div(g_nof_in,g_nof_out) -1);
+      snk_out_arr(i).ready  <= '1';
+      WAIT FOR c_clk_period;
+    END PROCESS;
+
+  END GENERATE;
+
+  -----------------------------------------------------------------------------
+  -- DUT
+  -----------------------------------------------------------------------------
+  u_reinterleave : ENTITY work.dp_reinterleave
+  GENERIC MAP (
+    g_nof_in         => g_nof_in,
+    g_deint_block_size  => g_deint_block_size,
+    g_nof_out        => g_nof_out,
+    g_inter_block_size => g_inter_block_size,
+    g_dat_w          => g_dat_w,
+    g_use_complex    => g_use_complex,
+    g_align_out => g_align_out
+  )
+  PORT MAP (
+    rst        => rst,
+    clk        => clk,
+    
+    snk_in_arr  => snk_in_arr, 
+    src_out_arr => src_out_arr
+  );
+
+END rtl;