processed review comments

libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd

@@ -141,7 +141,7 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
     fill_cipo_arr        : t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0);  -- used combinatorial to contain rd_cipo_arr from buffer or replacement data
     out_bsn              : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);  -- hold BSN until next sop, for easy view in Wave window
     out_channel_arr      : t_channel_arr(g_nof_streams-1 DOWNTO 0);  -- hold channel until next sop per stream, for easy view in Wave window
-    replace_cnt_en       : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+    replace_cnt_en_arr   : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
   END RECORD;
 
   -- Wires and auxiliary variables in p_comb
@@ -202,9 +202,9 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
 
   -- Counter signals
 
-  SIGNAL replace_cnt                 : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
-  SIGNAL nxt_stream_replaced_cnt_arr : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
-  SIGNAL i_stream_replaced_cnt_arr   : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL replace_cnt_arr          : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL nxt_hold_replace_cnt_arr : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL hold_replace_cnt_arr     : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
 
   -- Debug signals
   SIGNAL dbg_nof_streams            : NATURAL := g_nof_streams;
@@ -242,7 +242,7 @@ BEGIN
     v := r;  -- state signals
     v.mm_sosi := func_dp_stream_reset_control(r.mm_sosi);
     v.wr_copi_arr := RESET_MEM_COPI_CTRL(r.wr_copi_arr);
-    v.replace_cnt_en := (OTHERS => '0');
+    v.replace_cnt_en_arr := (OTHERS => '0');
 
     ----------------------------------------------------------------------------
     -- p_write_arr
@@ -307,13 +307,13 @@ BEGIN
         v.mm_sosi.channel := (OTHERS=>'0');
         FOR I IN 0 TO g_nof_streams-1 LOOP
           w.lost_data_flags_arr(I) := NOT v.filled_arr(I)(v.rd_blk_pointer);
-          v.replace_cnt_en(I) := w.lost_data_flags_arr(I);
+          v.replace_cnt_en_arr(I) := w.lost_data_flags_arr(I);
           IF stream_en_arr(I) = '1' THEN  -- use MM bit at sop
             v.use_replacement_data(I) := w.lost_data_flags_arr(I);  -- enabled stream, so replace the data if the data was lost
             v.mm_sosi.channel(I) := w.lost_data_flags_arr(I);  -- enabled stream, so flag the data if the data was lost
           ELSE
             v.use_replacement_data(I) := '1';  -- disabled stream, so replace the data, but do not flag the data as lost
-            v.replace_cnt_en(I) := '1';
+            v.replace_cnt_en_arr(I) := '1';
           END IF;
         END LOOP;
       END IF;
@@ -476,22 +476,14 @@ BEGIN
       rst     => dp_rst,
       clk     => dp_clk,
       cnt_clr => in_sosi_arr_p(0).sync,
-      cnt_en  => r.replace_cnt_en(I),
-      count   => replace_cnt(I)
+      cnt_en  => r.replace_cnt_en_arr(I),
+      count   => replace_cnt_arr(I)
     );
   END GENERATE;
 
-  nxt_stream_replaced_cnt_arr <= replace_cnt WHEN in_sosi_arr_p(0).sync = '1' ELSE i_stream_replaced_cnt_arr; 
-
-  p_cnt_replace : PROCESS(dp_rst, dp_clk)
-  BEGIN
-    IF dp_rst = '1' THEN
-      i_stream_replaced_cnt_arr <= (OTHERS => (OTHERS => '0'));
-    ELSIF rising_edge(dp_clk) THEN
-      i_stream_replaced_cnt_arr <= nxt_stream_replaced_cnt_arr;
-    END IF;
-  END PROCESS;
-  stream_replaced_cnt_arr <= i_stream_replaced_cnt_arr;
+  nxt_hold_replace_cnt_arr <= replace_cnt_arr WHEN in_sosi_arr_p(0).sync = '1' ELSE hold_replace_cnt_arr; 
+  hold_replace_cnt_arr     <= nxt_hold_replace_cnt_arr WHEN rising_edge(dp_clk);
+  stream_replaced_cnt_arr  <= hold_replace_cnt_arr;
   
   ------------------------------------------------------------------------------
   -- Pipelining

libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd

@@ -218,17 +218,17 @@ BEGIN
   -- statements where g_use_dual_clock = FALSE / TRUE will never be active simultaneously as a GENERATE statement cannot have an ELSE statement.
   rd_eop_cnt <= TO_UINT(reg_rd_eop_cnt) WHEN g_use_dual_clock ELSE wr_eop_cnt;
 
-  p_eop_cnt_comb: PROCESS(wr_eop_cnt, wr_eop_new, wr_eop_busy, wr_eop_done, snk_in)
-    VARIABLE v_wr_eop_cnt: NATURAL;
-    VARIABLE v_wr_eop_new: STD_LOGIC;
-    VARIABLE v_wr_eop_busy: STD_LOGIC;
-  BEGIN
-    -- We need to control in_new signal for common_reg_cross_domain. We can simply pulse in_new after in_done = '1'.
-    -- After we have send the wr_eop_cnt accross the clock domain by seting wr_eop_new, the wr_eop_cnt is reset to 0.
-    -- It is not possible to set in_new = snk_in.eop as there can be more snk_in.eop during the clock cross time necessary by common_reg_cross_domain.
-    v_wr_eop_new := wr_eop_new;
-    v_wr_eop_busy := wr_eop_busy;
-    IF g_use_dual_clock THEN 
+  gen_dual_clk : IF g_use_dual_clock = TRUE GENERATE
+    p_eop_cnt_comb_dc: PROCESS(wr_eop_cnt, wr_eop_new, wr_eop_busy, wr_eop_done, snk_in)
+      VARIABLE v_wr_eop_cnt: NATURAL;
+      VARIABLE v_wr_eop_new: STD_LOGIC;
+      VARIABLE v_wr_eop_busy: STD_LOGIC;
+    BEGIN
+      -- We need to control in_new signal for common_reg_cross_domain. We can simply pulse in_new after in_done = '1'.
+      -- After we have send the wr_eop_cnt accross the clock domain by seting wr_eop_new, the wr_eop_cnt is reset to 0.
+      -- It is not possible to set in_new = snk_in.eop as there can be more snk_in.eop during the clock cross time necessary by common_reg_cross_domain.
+      v_wr_eop_new := wr_eop_new;
+      v_wr_eop_busy := wr_eop_busy;
       v_wr_eop_cnt := wr_eop_cnt; 
       
       -- When done = 1, busy can be set to 0.
@@ -240,30 +240,35 @@ BEGIN
         v_wr_eop_busy := '1';
         v_wr_eop_new := '1'; 
       END IF; 
-  
+    
       -- After we transfered wr_eop_cnt, we can reset it to 0.
       IF wr_eop_new = '1' THEN
         v_wr_eop_new := '0';
         v_wr_eop_cnt := 0;
       END IF;
-  
+    
       -- Count incoming snk_in.eop
       IF snk_in.eop = '1' THEN 
         v_wr_eop_cnt := v_wr_eop_cnt + 1;
       END IF;
+  
       nxt_wr_eop_cnt <= v_wr_eop_cnt;
+      nxt_wr_eop_new <= v_wr_eop_new;
+      nxt_wr_eop_busy <= v_wr_eop_busy;
+    END PROCESS; 
+  END GENERATE;
 
+  gen_single_clk : IF g_use_dual_clock = FALSE GENERATE
     -- No need to transfer eop counter across clock domains for single clock
-    ELSE 
+    p_eop_cnt_comb_sc: PROCESS(snk_in)
+    BEGIN
       IF snk_in.eop = '1' THEN
         nxt_wr_eop_cnt <= 1; -- wr_eop_cnt can simply be set to 1 instead of counting as it is immidiatly processed due to having a single clock.
       ELSE
         nxt_wr_eop_cnt <= 0;
       END IF; 
-    END IF;
-    nxt_wr_eop_new <= v_wr_eop_new;
-    nxt_wr_eop_busy <= v_wr_eop_busy;
-  END PROCESS; 
+    END PROCESS; 
+  END GENERATE;
 
   p_eop_cnt_clk: PROCESS(wr_clk, wr_rst)
   BEGIN