yup

applications/lofar2/libraries/ddrctrl/hdllib.cfg

@@ -11,6 +11,7 @@ synth_files =
     src/vhdl/ddrctrl_input.vhd
     src/vhdl/ddrctrl_controller.vhd
     src/vhdl/ddrctrl.vhd
+    src/vhdl/ddrctrl_pkg.vhd
 
 test_bench_files =
     tb/vhdl/tb_ddrctrl_input_address_counter.vhd

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd

@@ -32,7 +32,7 @@
 --  https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
 --  The maximum value of the address is determend by g_tech_ddr.
 
-LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, io_ddr_lib;
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, io_ddr_lib, lofar2_ddrctrl_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE technology_lib.technology_pkg.ALL;
@@ -42,6 +42,7 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE io_ddr_lib.ALL;
+USE lofar2_ddrctrl_lib.ddrctrl_pkg.ALL;
 
 
 ENTITY ddrctrl IS
@@ -50,7 +51,8 @@ ENTITY ddrctrl IS
     g_sim_model       : BOOLEAN                                             := TRUE;                                          -- determens if this is a simulation
     g_technology      : NATURAL                                             := c_tech_select_default;
     g_nof_streams     : NATURAL                                             := 12;                                            -- number of input streams
-    g_data_w          : NATURAL                                             := 14                                             -- data with of input data vectors
+    g_data_w          : NATURAL                                             := 14;                                            -- data with of input data vectors
+    g_stop_pos        : t_c_stop_pos
    );
   PORT (
     clk               : IN  STD_LOGIC                                       := '0';
@@ -193,7 +195,8 @@ BEGIN
   -- controller of ddrctrl
   u_ddrctrl_controller : ENTITY work.ddrctrl_controller
   GENERIC MAP(
-    g_tech_ddr                => g_tech_ddr
+    g_tech_ddr                => g_tech_ddr,
+    g_stop_pos                => g_stop_pos
   )
   PORT MAP(
   clk                         => clk,

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd

@@ -27,18 +27,20 @@
 --  https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
 --  
 
-LIBRARY IEEE, dp_lib, common_lib, tech_ddr_lib;
+LIBRARY IEEE, dp_lib, common_lib, tech_ddr_lib, lofar2_ddrctrl_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_pkg.ALL;
 USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE lofar2_ddrctrl_lib.ddrctrl_pkg.ALL;
 
 
 ENTITY ddrctrl_controller IS
   GENERIC (
-    g_tech_ddr  : t_c_tech_ddr
+    g_tech_ddr  : t_c_tech_ddr;
+    g_stop_pos  : t_c_stop_pos
   );
   PORT (
     clk	     	  : IN  STD_LOGIC;
@@ -68,7 +70,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
   CONSTANT  c_zeros           : STD_LOGIC_VECTOR(c_bitshift_adr-1 DOWNTO 0) := (OTHERS => '0');
 
   -- type for statemachine
-  TYPE t_state IS (RESET, WRITING, STOP_WRITING, READING, STOP_READING, IDLE);
+  TYPE t_state IS (RESET, WRITING, SET_STOP, STOP_WRITING, READING, STOP_READING, IDLE);
 
   -- record for readability
   TYPE t_reg IS RECORD
@@ -123,24 +125,60 @@ BEGIN
       ELSE
         v.dvr_mosi.burstbegin := '0';
       END IF;
-    v.dvr_mosi.burstsize  := TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
-    v.dvr_mosi.wr         := '1';
-    v.dvr_mosi.rd         := '0';
+      v.dvr_mosi.burstsize  := TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
+      v.dvr_mosi.wr         := '1';
+      v.dvr_mosi.rd         := '0';
+      v.wr_sosi             := out_sosi;
 
 
 
-    WHEN STOP_WRITING =>
-      IF (out_adr + (c_max_adr / 2)  >= c_max_adr) THEN
-        v.stop_adr := out_adr - (c_max_adr / 2);
-      ELSE
-        v.stop_adr := out_adr + (c_max_adr / 2);
+    WHEN SET_STOP =>
+      --setting a stop address dependend on the g_stop_pos
+      IF g_stop_pos=START THEN
+        v.stop_adr := 0;
+      END IF;
+
+      IF g_stop_pos=HALFWAY THEN
+        IF (out_adr + (c_max_adr / 2)  >= c_max_adr) THEN
+          v.stop_adr := out_adr - (c_max_adr / 2);
+        ELSE
+          v.stop_adr := out_adr + (c_max_adr / 2);
+        END IF;
+        IF (stop_in = '1' AND out_adr = v.stop_adr) THEN
+          --stop_out <= '1';
+          v.dvr_mosi.address := TO_UVEC(out_adr, dvr_mosi.address'length);
+        ELSE
+          --stop_out <= '0';
+        END IF;
+      END IF;
+
+      IF g_stop_pos=IMMIDIATE THEN
+        v.stop_adr := c_max_adr;
       END IF;
-      IF (stop_in = '1' AND out_adr = v.stop_adr) THEN
-        --stop_out <= '1';
-        v.dvr_mosi.address := TO_UVEC(out_adr, dvr_mosi.address'length);
+
+
+      -- still a write cyle
+      IF TO_UVEC(out_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN                        -- adr mod 64 = 0
+        v.dvr_mosi.burstbegin := '1';
+        IF out_adr = 0 THEN
+          v.dvr_mosi.address    := TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
+        ELSE
+          v.dvr_mosi.address    := TO_UVEC(out_adr-c_burstsize, dvr_mosi.address'length);
+        END IF;
       ELSE
-        --stop_out <= '0';
+        v.dvr_mosi.burstbegin := '0';
       END IF;
+      v.dvr_mosi.burstsize  := TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
+      v.dvr_mosi.wr         := '1';
+      v.dvr_mosi.rd         := '0';
+      v.wr_sosi             := out_sosi;
+
+
+
+    WHEN STOP_WRITING =>
+      v.stopped             := '0';
+      v.wr_sosi.valid       := '0';
+      -- enable flush
 
 
 
@@ -154,16 +192,16 @@ BEGIN
     IF rst = '1' THEN
       v.state := RESET;
     ELSIF stop_in = '1' THEN
-      v.state := STOP_WRITING;
+      v.state := SET_STOP;
     ELSE
       v.state := WRITING;
     END IF;
-    d_reg <= v;
+    d_reg     <= v;
   END PROCESS;
 
   -- fill outputs
   dvr_mosi  <= q_reg.dvr_mosi;
   wr_sosi   <= q_reg.wr_sosi;
-  rd_siso    <= q_reg.rd_siso;
+  rd_siso   <= q_reg.rd_siso;
 
 END rtl;

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd

@@ -22,7 +22,7 @@
 -- Usage:
 -- > run -a
 
-LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
+LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib, lofar2_ddrctrl_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE IEEE.MATH_REAL.ALL;
@@ -32,6 +32,8 @@ USE dp_lib.dp_stream_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
+USE lofar2_ddrctrl_lib.ddrctrl_pkg.ALL;
+
 
 ENTITY tb_ddrctrl IS
   GENERIC (
@@ -43,7 +45,8 @@ ENTITY tb_ddrctrl IS
     g_sim_length              : NATURAL                                               := 16500;                                   -- close to the amount of word that gets put into the memory
     g_technology              : NATURAL                                               := c_tech_select_default;
     g_tech_ddr3               : t_c_tech_ddr                                          := c_tech_ddr3_4g_800m_master;
-    g_tech_ddr4               : t_c_tech_ddr                                          := c_tech_ddr4_4g_1600m
+    g_tech_ddr4               : t_c_tech_ddr                                          := c_tech_ddr4_4g_1600m;
+    g_stop_pos                : t_c_stop_pos                                            := HALFWAY
   );
 END tb_ddrctrl;
 
@@ -161,7 +164,8 @@ BEGIN
     g_sim_model       => g_sim_model,
     g_technology      => g_technology,
     g_nof_streams     => g_nof_streams,
-    g_data_w          => g_data_w
+    g_data_w          => g_data_w,
+    g_stop_pos        => g_stop_pos
   )
   PORT MAP (
     clk               => clk,