SVN copied dp_xonoff.vhd to RadioHDL and added g_bypass.

libraries/base/dp/hdllib.cfg

@@ -16,7 +16,7 @@ synth_files =
     $UNB/Firmware/modules/dp/src/vhdl/dp_eop_extend.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_validate.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_ready.vhd
-    $UNB/Firmware/modules/dp/src/vhdl/dp_xonoff.vhd
+    src/vhdl/dp_xonoff.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_flush.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_latency_increase.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_latency_adapter.vhd

libraries/base/dp/src/vhdl/dp_xonoff.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Add flow XON-XOFF control by flushing frames
+-- Description:
+--   When g_bypass=TRUE then the in and out are wired and the component is void.
+--   When g_bypass=FALSE then:
+--     The output is ON when flush='0'.
+--     The output is OFF when flush='1'.
+--     The transition from OFF to ON occurs after an in_sosi.eop so between frames
+--     The transition from ON to OFF occurs after an in_sosi.eop so between frames
+-- Remark:
+-- . The output controls are not registered.
+-- . The xon timing is not cycle critical therefor register flush to ease
+--   timing closure
+-- . Originally based on rad_frame_onoff from LOFAR RSP firmware
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_xonoff IS
+  GENERIC (
+    g_bypass : BOOLEAN := FALSE
+  );
+  PORT (
+    rst           : IN  STD_LOGIC;
+    clk           : IN  STD_LOGIC;
+    -- Frame in
+    in_siso       : OUT t_dp_siso;
+    in_sosi       : IN  t_dp_sosi;
+    -- Frame out
+    out_siso      : IN  t_dp_siso;  -- flush control via out_siso.xon
+    out_sosi      : OUT t_dp_sosi
+  );
+END dp_xonoff;
+
+
+ARCHITECTURE rtl OF dp_xonoff IS
+
+  SIGNAL flush      : STD_LOGIC;
+  SIGNAL nxt_flush  : STD_LOGIC;
+  
+  SIGNAL out_en     : STD_LOGIC;
+  SIGNAL nxt_out_en : STD_LOGIC;
+  
+BEGIN
+
+  gen_bypass : IF g_bypass=TRUE GENERATE
+    in_siso  <= out_siso;
+    out_sosi <= in_sosi;
+  END GENERATE;
+  
+  no_bypass : IF g_bypass=FALSE GENERATE
+    in_siso   <= out_siso;           -- pass on ready for detailed flow control per cycle
+    nxt_flush <= NOT out_siso.xon;   -- use xon for flow control at frame level
+  
+    p_clk: PROCESS(clk, rst)
+    BEGIN
+      IF rst='1' THEN
+        flush  <= '0';
+        out_en <= '1';
+      ELSIF rising_edge(clk) THEN
+        flush  <= nxt_flush;     -- pipeline register flush to ease timing closure
+        out_en <= nxt_out_en;    -- state register out_en because it can only change between frames
+      END IF;
+    END PROCESS;
+    
+    p_out_en : PROCESS(flush, out_en, in_sosi)
+    BEGIN
+      nxt_out_en <= out_en;
+      IF in_sosi.eop='1' THEN
+        IF flush='1' THEN
+          nxt_out_en <= '0';
+        ELSE
+          nxt_out_en <= '1';
+        END IF;
+      END IF;    
+    END PROCESS;
+    
+    p_out_sosi : PROCESS(in_sosi, out_en)
+    BEGIN
+      -- Pass on sosi data via wires
+      out_sosi       <= in_sosi;
+      
+      -- XON/XOFF flow control via sosi control
+      out_sosi.sync  <= in_sosi.sync  AND out_en;
+      out_sosi.valid <= in_sosi.valid AND out_en;
+      out_sosi.sop   <= in_sosi.sop   AND out_en;
+      out_sosi.eop   <= in_sosi.eop   AND out_en;
+    END PROCESS;
+  END GENERATE;
+  
+END ARCHITECTURE;