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hdl_lib_name = compaan_unb1_10g_bunny_static_split
hdl_library_clause_name = compaan_unb1_10g_bunny_static_split_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag tr_10GbE bunny_static_split
hdl_lib_technology = ip_stratixiv
synth_files =
src/vhdl/compaan_design.vhd
src/vhdl/mmm_compaan_unb1_10g_bunny_static_split.vhd
src/vhdl/compaan_unb1_10g_bunny_static_split.vhd
$RADIOHDL/applications/compaan/designs/compaan_unb1_10g_bg_db/src/vhdl/mmm_compaan_unb1_10g_bg_db.vhd
$RADIOHDL/applications/compaan/designs/compaan_unb1_10g_bg_db/src/vhdl/compaan_unb1_10g_bg_db.vhd
test_bench_files =
tb/vhdl/tb_compaan_unb1_10g_bunny_static_split.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = quartus/qsys_compaan_unb1_10g_bunny_static_split.qsys .
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/compaan_unb1_10g_bunny_static_split_pins.tcl
quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/compaan_unb1_10g_bunny_static_split/qsys_compaan_unb1_10g_bunny_static_split/synthesis/qsys_compaan_unb1_10g_bunny_static_split.qip
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
mmm_name = compaan_unb1_10g_bunny_static_split
board_select = unb1
custom_peripherals =
reg_bsn_monitor 4 4
reg_dp_offload_tx 1 1
reg_dp_offload_tx_hdr_dat 1 6
reg_dp_offload_tx_hdr_ovr 1 5
reg_dp_offload_rx_hdr_dat 1 7
reg_dp_offload_rx_filter_hdr_fields 1 7
reg_diag_data_buffer 1 5
ram_diag_data_buffer 1 14
reg_diag_bg 1 3
ram_diag_bg 1 9
reg_mdio_0 1 3
reg_mdio_1 1 3
reg_mdio_2 1 3
reg_tr_10gbe 1 15
reg_tr_xaui 1 11
reg_compaan 1 19
input_clks = mm_clk
synth_master = qsys
vhdl_output_path = src/vhdl/
###############################################################################
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs_clk.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs_0.tcl
------------------------------------------------------------------
-- TOP LEVEL
------------------------------------------------------------------
library IEEE, dp_lib, bunny_static_split_lib;
use IEEE.STD_LOGIC_1164.ALL;
USE dp_lib.dp_stream_pkg.ALL;
entity compaan_design is
generic (
BLOCKS_PER_SYNC : natural := 10
);
port (
-- ST sink
snk_out : OUT t_dp_siso := c_dp_siso_rdy;
snk_in : IN t_dp_sosi;
-- ST source
src_in : IN t_dp_siso;
src_out : OUT t_dp_sosi;
TEST_STOP : out std_logic_vector(2 downto 0 );
TEST_ERROR : out std_logic_vector(2 downto 0 );
TEST_FIFO_FULL : out std_logic_vector(1 downto 0 );
TEST_BLOCK_RD : out std_logic_vector(2 downto 0 );
address : in std_logic_vector(18 downto 0 );
read_data : out std_logic_vector(31 downto 0 );
read_en : in std_logic;
write_en : in std_logic;
write_data : in std_logic_vector(31 downto 0 );
MM_CLK : in std_logic;
KPN_CLK : in std_logic;
KPN_RST : in std_logic
);
end compaan_design;
architecture STRUCTURE of compaan_design is
signal data_in_Data : std_logic_vector(63 downto 0);
signal data_in_control : std_logic;
signal data_in_Read : std_logic;
signal data_in_Exists : std_logic;
signal data_in_SOP : std_logic;
signal data_in_EOP : std_logic;
signal data_out_Data_c : std_logic_vector(63 downto 0);
signal data_out_Control_c : std_logic;
signal data_out_Write_c : std_logic;
signal data_out_Data : std_logic_vector(63 downto 0);
signal data_out_Control : std_logic;
signal data_out_Write : std_logic;
signal data_out_Full : std_logic;
signal data_out_SOP : std_logic;
signal data_out_EOP : std_logic;
signal snk_in_nop : t_dp_sosi := c_dp_sosi_rst;
begin
snk_out.ready <= data_in_Read; --'1';
-- wrapper -> ipcore
data_in_Data <= snk_in.data(63 downto 0);
data_in_Exists <= snk_in.valid;
data_in_SOP <= snk_in.sop;
data_in_EOP <= snk_in.eop;
-- ipcore --> wrapper
--src_out.valid <= data_out_Write;
--src_out.data <= RESIZE_DP_DATA(data_out_Data);
--src_out.sop <= data_out_SOP;
--src_out.eop <= data_out_EOP;
snk_in_nop.valid <= data_out_Write_c;
snk_in_nop.data <= RESIZE_DP_DATA(data_out_Data_c);
data_out_Full <= not src_in.ready;
-- Compaan ipcore
u_compaan_design : ENTITY bunny_static_split_lib.bunny_static_split
PORT MAP (
data_in_Data => data_in_Data,
data_in_Control => data_in_Control,
data_in_Read => data_in_Read,
data_in_Exists => data_in_Exists,
data_out_Data => data_out_Data_c,
data_out_Control => data_out_Control_c,
data_out_Write => data_out_Write_c,
data_out_Full => data_out_Full,
TEST_STOP => open,
TEST_ERROR => open,
TEST_FIFO_FULL => open,
TEST_BLOCK_RD => open,
address => address,
read_data => read_data,
read_en => read_en,
write_en => write_en,
write_data => write_data,
pci_clk => MM_CLK,
-- MM_RST => MM_RST,
KPN_CLK => KPN_CLK,
KPN_RST => KPN_RST
);
u_pkg_signals_gen : ENTITY dp_lib.dp_block_gen
GENERIC MAP (
g_use_src_in => FALSE, -- when true use src_in.ready else use snk_in.valid for flow control
g_nof_data => BLOCKS_PER_SYNC -- nof data per block
)
port map (
rst => KPN_RST,
clk => KPN_CLK,
-- Streaming sink
snk_in => snk_in_nop,
-- Streaming source
src_in => src_in,
src_out => src_out,
-- MM control
en => '1'
);
end architecture STRUCTURE;
#! /usr/bin/env python
###############################################################################
#
# Copyright (dC) 2015
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
# Purpose:
# . Scripts make 10G settings for FN0 and FN1:
#
# Where FN0 and FN1 contain both the compaan_unb1_10g_bg_db design.
#
# Description:
# . BG outputs blocks of 365 64b words = 2920 bytes;
# . BG uses inter-block gap size of c_gap_size = 3000 words to limit BG output rate to
# Usage:
# . Load the following images on the following nodes:
# . FN0 - compaan_unb1_10g_loopback or compaan_unb1_10g_compaan
# . FN1 - compaan_unb1_10g_blockgen
# . python tc_compaan_unb1_10g_bg_lb.py --unb # --fn 0,1
# . Use tcpdump to view the received packets.
# FN2 = lcu(bg and db), FN3 = dut(app)
from common import *
import test_case
import node_io
import pi_dp_offload_tx_hdr_dat_compaan_unb1_10g_bg_db
import pi_dp_offload_rx_hdr_fields_compaan_unb1_10g_bg_db
import pi_diag_block_gen
import pi_diag_data_buffer
import pi_eth
import pi_compaan
from eth import *
# Some definitions
c_10g_data_w = 64 # 64 bit internal data
c_blocksize = 16 # 365 samples * 8 bytes(= 64bit) = 2920 bytes
c_bg_nof_streams = 1
c_bg_ram_size = 512
c_gap_size = 100
c_nof_blocks_per_sync = 10
c_write_block_gen = True
# Instantiate testcase and IO
tc = test_case.Testcase('TB - ', '')
io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
ca = pi_compaan.PiCompaan(tc, io, nof_inst=1)
# rx fields reg
rx_filter_hdr = pi_dp_offload_rx_hdr_fields_compaan_unb1_10g_bg_db.PiDpOffloadRxFilterHdrFieldsCompaanUnb110gBgDb(tc, io, nof_inst=1)
# Instantiate 10G offload objects: FN0=[0], FN1=[1]
dpotx_hdr_dat = pi_dp_offload_tx_hdr_dat_compaan_unb1_10g_bg_db.PiDpOffloadTxHdrDatCompaanUnb110GBgDb(tc, io, nof_inst=1)
# Create block generator/data buffer instance (only FN2)
bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, c_bg_nof_streams, c_bg_ram_size, tc.nodeFn2Nrs )
db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = '', nofStreams=c_bg_nof_streams, ramSizePerStream=2048, nodeNr = tc.nodeFn2Nrs )
# MAC Addresses
eth_src_mac = 0x2286080008 # 10G MAC base address for UniBoard
eth_dst_mac = 0x074306C700 #+ 1 # 10G MAC address jop63
# Fixed header constants
IP_HEADER_LENGTH = 20
UDP_HEADER_LENGTH = 8
USR_HEADER_LENGTH = 20
USR_HDR_WORD_ALIGN = 2
NOF_PAYLOAD_BYTES = c_blocksize * 8 #2920
###############################################################################
# The IP header field values. All fixed except ip_src_addr
# (and concequently the ip_header_checksum).
###############################################################################
ip_version = 4
ip_header_length = 5 # 5 32b words
ip_services = 0
ip_total_length = IP_HEADER_LENGTH+UDP_HEADER_LENGTH+USR_HEADER_LENGTH+USR_HDR_WORD_ALIGN+NOF_PAYLOAD_BYTES - 7 # 6196B
ip_identification = 0
ip_flags = 2
ip_fragment_offset = 0
ip_time_to_live = 127
ip_protocol = 17
ip_header_checksum = 0 # to be calculated
#ip_src_addr_fn0 = 0xc0a80164 # 0xc0a80164 = 192.168.1.100
#ip_src_addr_fn1 = 0xc0a80165 # 0xc0a80165 = 192.168.1.101
ip_src_addr_fn2 = 0xc0a80166 # 0xc0a80164 = 192.168.1.102
ip_src_addr_fn3 = 0xc0a80167 # 0xc0a80165 = 192.168.1.103
ip_dst_addr = 0xc0a80102 # 0xc0a80102 = 192.168.1.2 = IP-address 10G in jop63
###############################################################################
# Calculate and print the IP header checksum for FN0
###############################################################################
hdr_bits_common = CommonBits(ip_version ,4) & \
CommonBits(ip_header_length ,4) & \
CommonBits(ip_services ,8) & \
CommonBits(ip_total_length ,16) & \
CommonBits(ip_identification ,16) & \
CommonBits(ip_flags ,3) & \
CommonBits(ip_fragment_offset ,13) & \
CommonBits(ip_time_to_live ,8) & \
CommonBits(ip_protocol ,8) & \
CommonBits(ip_header_checksum ,16)
#hdr_bits_fn0 = hdr_bits_common & \
# CommonBits(ip_src_addr_fn0 ,32) & \
# CommonBits(ip_dst_addr ,32)
#hdr_bits_fn1 = hdr_bits_common & \
# CommonBits(ip_src_addr_fn1 ,32) & \
# CommonBits(ip_dst_addr ,32)
hdr_bits_fn2 = hdr_bits_common & \
CommonBits(ip_src_addr_fn2 ,32) & \
CommonBits(ip_dst_addr ,32)
hdr_bits_fn3 = hdr_bits_common & \
CommonBits(ip_src_addr_fn3 ,32) & \
CommonBits(ip_dst_addr ,32)
#hdr_bytes_fn0 = CommonBytes(hdr_bits_fn0.data, 20)
#hdr_bytes_fn1 = CommonBytes(hdr_bits_fn1.data, 20)
hdr_bytes_fn2 = CommonBytes(hdr_bits_fn2.data, 20)
hdr_bytes_fn3 = CommonBytes(hdr_bits_fn3.data, 20)
#tc.append_log(3, 'IP header checksum FN0: %d' % ip_hdr_checksum(hdr_bytes_fn0))
#tc.append_log(3, 'IP header checksum FN1: %d' % ip_hdr_checksum(hdr_bytes_fn1))
tc.append_log(3, 'IP header checksum FN2: %d' % ip_hdr_checksum(hdr_bytes_fn2))
tc.append_log(3, 'IP header checksum FN3: %d' % ip_hdr_checksum(hdr_bytes_fn3))
#hdr_bits = CommonBits(ip_version ,4) & \
# CommonBits(ip_header_length ,4) & \
# CommonBits(ip_services ,8) & \
# CommonBits(ip_total_length ,16) & \
# CommonBits(ip_identification ,16) & \
# CommonBits(ip_flags ,3) & \
# CommonBits(ip_fragment_offset ,13) & \
# CommonBits(ip_time_to_live ,8) & \
# CommonBits(ip_protocol ,8) & \
# CommonBits(ip_header_checksum ,16) & \
# CommonBits(ip_src_addr_fn0 ,32) & \
# CommonBits(ip_dst_addr ,32)
#
#hdr_bytes = CommonBytes(hdr_bits.data, 20)
#
#print ip_hdr_checksum(hdr_bytes)
# Write setting for the block generator:
#ca.write(node_nrs=tc.nodeNrs[1],registers=[('register_name_0', 15)])
#ca.write(node_nrs=tc.nodeNrs[1],registers=[('register_name_4', 20)])
bg.write_block_gen_settings(samplesPerPacket=c_blocksize, blocksPerSync=c_nof_blocks_per_sync, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
# Configure 10G of FN2
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('eth_src_mac', eth_src_mac + 2)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac', eth_dst_mac)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('ip_src_addr', ip_src_addr_fn2)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr', ip_dst_addr)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('ip_header_checksum', ip_hdr_checksum(hdr_bytes_fn2))], regmap=dpotx_hdr_dat.regmap)
# Configure 10G of FN3
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('eth_src_mac', eth_src_mac + 3)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac', eth_dst_mac)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_src_addr', ip_src_addr_fn3)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr', ip_dst_addr)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_header_checksum', ip_hdr_checksum(hdr_bytes_fn3))], regmap=dpotx_hdr_dat.regmap)
# Configure rx filter
rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac', eth_src_mac + 3)], regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr', ip_src_addr_fn3)], regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('udp_dst_port', 4000)], regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_total_length', ip_total_length)],regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac_ena', 0)], regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr_ena', 0)], regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_total_length_ena', 0)], regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('udp_dst_port_ena', 0)], regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac_ena', 0)], regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr_ena', 0)], regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('ip_total_length_ena', 0)], regmap=rx_filter_hdr.regmap)
rx_filter_hdr.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('udp_dst_port_ena', 0)], regmap=rx_filter_hdr.regmap)
################################################################################
##
## Write data and settings to block generator
##
################################################################################
# Write setting for the block generator:
bg.write_block_gen_settings(samplesPerPacket=c_blocksize+1, blocksPerSync=c_nof_blocks_per_sync, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
bg_data = []
#bg_data.append(0xC7000022)
for i in range(c_bg_ram_size):
bg_data.append(i)
# Write the stimuli to the block generator and enable the block generator
if c_write_block_gen == True:
for i in range(c_bg_nof_streams):
bg.write_waveform_ram(data=bg_data, channelNr= i)
# BG: Enable the blockgenerator
bg.write_enable()
################################################################################
##
## Read data from the databuffer
##
################################################################################
#time.sleep(10)
db_out = []
#ca.read(node_nrs=tc.nodeNrs[1],registers='register_name_0')
do_until_ge(db.read_nof_words, ms_retry=1000, val=1024, s_timeout=3600)
for i in range(1):
db_out.append(flatten(db.read_data_buffer(streamNr=i, n=2048, radix='uns', width=64, nofColumns=1))) #n=2048 (32 bit word) = 1024 (64 bit word)
print db_out
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose:
-- . Test bench compaan_unb1_dp_offload.
-- Description:
-- . The block generator in the design is enabled by default.
-- . Design 'compaan_unb1_dp_offload' requires the 1GbE demux to be set up so
-- received streams are forwarded based on the received destination UDP port.
-- This is done by /tb/python/tc_unb1_board1_dp_offload.py.
-- Usage (manual mode, run compaan_unb1_dp_offload.py for auto mode):
-- . Start ModelSim
-- . lp compaan_unb1_dp_offload
-- . mk compile
-- . double click simulation configuration
-- . as 8
-- . run 2us (wait until MM master did the initial ETH settings before Python ETH access)
-- . in separate console: python tc_unb1_board1_dp_offload.py --unb 0 --fn 0 -r 0:2 --sim
-- . run -a
LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_compaan_unb1_10g_bunny_static_split IS
END tb_compaan_unb1_10g_bunny_static_split;
ARCHITECTURE tb OF tb_compaan_unb1_10g_bunny_static_split IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_unb1_board_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr_bg_db : NATURAL := 2; -- FN2
CONSTANT c_node_nr_app : NATURAL := 3; -- FN3
CONSTANT c_id_bg_db : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr_bg_db, c_unb1_board_nof_chip_w);
CONSTANT c_id_app : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr_app, c_unb1_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_eth_clk_period : TIME := 40 ns;
CONSTANT c_sa_clk_period : TIME := 6.4 ns;
CONSTANT c_clk_period : TIME := 5 ns;
SIGNAL clk : STD_LOGIC := '0';
SIGNAL sa_clk : STD_LOGIC := '1';
SIGNAL eth_clk : STD_LOGIC := '0';
SIGNAL eth_txp : STD_LOGIC;
SIGNAL eth_rxp : STD_LOGIC;
SIGNAL si_fn_0_lcu_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL si_fn_1_lcu_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL si_fn_2_lcu_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL si_fn_3_lcu_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL si_fn_0_lcu_rx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL si_fn_1_lcu_rx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL si_fn_2_lcu_rx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL si_fn_3_lcu_rx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
SIGNAL ID_bg_db : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id_bg_db;
SIGNAL ID_app : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id_app;
BEGIN
----------------------------------------------------------------------------
-- Externally generated clocks
----------------------------------------------------------------------------
clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2;
------------------------------------------------------------------------------
-- u_lcu
------------------------------------------------------------------------------
u_lcu : ENTITY work.compaan_unb1_10g_bg_db
GENERIC MAP (
g_sim => c_sim,
g_sim_unb_nr => c_unb1_board_nr,
g_sim_node_nr => c_node_nr_bg_db
)
PORT MAP (
CLK => clk,
PPS => '0',
VERSION => VERSION,
ID => ID_bg_db,
-- 1GbE Control Interface
ETH_clk => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
-- Transceiver clocks
SA_CLK => sa_clk,
-- Serial I/O
SI_FN_0_RX => si_fn_0_lcu_rx,
SI_FN_1_RX => si_fn_1_lcu_rx,
SI_FN_2_RX => si_fn_2_lcu_rx,
SI_FN_3_RX => si_fn_3_lcu_rx,
SI_FN_0_TX => si_fn_0_lcu_tx,
SI_FN_1_TX => si_fn_1_lcu_tx,
SI_FN_2_TX => si_fn_2_lcu_tx,
SI_FN_3_TX => si_fn_3_lcu_tx
);
------------------------------------------------------------------------------
-- u_dut
------------------------------------------------------------------------------
u_dut : ENTITY work.compaan_unb1_10g_bunny_static_split
GENERIC MAP (
g_sim => c_sim,
g_sim_unb_nr => c_unb1_board_nr,
g_sim_node_nr => c_node_nr_app
)
PORT MAP (
CLK => clk,
PPS => '0',
VERSION => VERSION,
ID => ID_app,
-- 1GbE Control Interface
ETH_clk => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
-- Transceiver clocks
SA_CLK => sa_clk,
-- Serial I/O
SI_FN_0_RX => si_fn_0_lcu_tx,
SI_FN_1_RX => si_fn_1_lcu_tx,
SI_FN_2_RX => si_fn_2_lcu_tx,
SI_FN_3_RX => si_fn_3_lcu_tx,
SI_FN_0_TX => si_fn_0_lcu_rx,
SI_FN_1_TX => si_fn_1_lcu_rx,
SI_FN_2_TX => si_fn_2_lcu_rx,
SI_FN_3_TX => si_fn_3_lcu_rx
);
END tb;
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