increased read latency of mms_dp_gain_serial_arr

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd

@@ -99,7 +99,7 @@ ARCHITECTURE str OF node_sdp_filterbank IS
   CONSTANT c_coefs_file_prefix : STRING := "data/Coeffs16384Kaiser-quant_1wb";
   CONSTANT c_gains_file_name : STRING := "data/gains_1024_complex_16b13f_unit"; -- Can be generated by src/python/sdp_hex.py
 
-  CONSTANT c_subband_equalizer_latency : NATURAL := 4;
+  CONSTANT c_subband_equalizer_latency : NATURAL := 5;
 
   CONSTANT c_nof_masters : POSITIVE := 2;
 

libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd

@@ -100,7 +100,7 @@ ARCHITECTURE str OF mms_dp_gain_serial_arr IS
   --   dat_w     : NATURAL;
   --   nof_dat   : NATURAL;    -- optional, nof dat words <= 2**adr_w
   --   init_sl   : STD_LOGIC;  -- optional, init all dat words to std_logic '0', '1' or 'X'
-  CONSTANT c_mm_ram : t_c_mem := (latency  => 1,
+  CONSTANT c_mm_ram : t_c_mem := (latency  => 2, -- set latency to 2 to ease timing
                                   adr_w    => ceil_log2(g_nof_gains),
                                   dat_w    => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
                                   nof_dat  => g_nof_gains,

libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd

@@ -57,7 +57,7 @@ ARCHITECTURE tb OF tb_mms_dp_gain_serial_arr IS
   CONSTANT c_mm_clk_period              : TIME := 20 ns;
   CONSTANT c_dp_clk_period              : TIME := 10 ns;
   CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
-  CONSTANT c_dut_latency                : NATURAL := 4;    -- = 3 for the real or complex multiplier + 1 for the RAM read latency
+  CONSTANT c_dut_latency                : NATURAL := 5;    -- = 3 for the real or complex multiplier + 2 for the RAM read latency
   
   CONSTANT c_real_multiply              : BOOLEAN := g_complex_data=FALSE AND g_complex_gain=FALSE;
   CONSTANT c_nof_gains_w                : NATURAL := ceil_log2(g_nof_gains);