Moved hdllib.cfg for dp, uth, i2c and ppsh from UniBoard to RadioHDL.

libraries/base/dp/hdllib.cfg

+hdl_lib_name = dp
+hdl_library_clause_name = dp_lib
+hdl_lib_uses = mm common easics
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    src/vhdl/dp_stream_pkg.vhd
+    src/vhdl/dp_packetizing_pkg.vhd
+    src/vhdl/dp_packet_pkg.vhd
+    
+    src/vhdl/dp_eop_extend.vhd
+    src/vhdl/dp_validate.vhd
+    src/vhdl/dp_ready.vhd
+    src/vhdl/dp_xonoff.vhd
+    src/vhdl/dp_flush.vhd
+    src/vhdl/dp_latency_increase.vhd
+    src/vhdl/dp_latency_adapter.vhd
+    src/vhdl/dp_hold_data.vhd
+    src/vhdl/dp_hold_ctrl.vhd
+    src/vhdl/dp_hold_input.vhd
+    src/vhdl/dp_pipeline.vhd
+    src/vhdl/dp_pipeline_ready.vhd
+    src/vhdl/dp_paged_sop_eop_reg.vhd
+    src/vhdl/dp_packet_detect.vhd
+    src/vhdl/dp_shiftreg.vhd
+    src/vhdl/dp_fifo_info.vhd
+    src/vhdl/dp_fifo_sc.vhd
+    src/vhdl/dp_fifo_fill.vhd
+    src/vhdl/dp_fifo_dc.vhd
+    src/vhdl/dp_fifo_dc_mixed_widths.vhd
+    src/vhdl/dp_fifo_to_mm.vhd
+    src/vhdl/dp_fifo_to_mm_reg.vhd
+    src/vhdl/dp_fifo_from_mm.vhd
+    src/vhdl/dp_fifo_from_mm_reg.vhd
+    src/vhdl/mms_dp_fifo_to_mm.vhd
+    src/vhdl/mms_dp_fifo_from_mm.vhd
+    src/vhdl/dp_mux.vhd
+    src/vhdl/dp_demux.vhd
+    src/vhdl/dp_loopback.vhd
+    src/vhdl/dp_concat.vhd
+    src/vhdl/dp_split.vhd
+    src/vhdl/dp_split_reg.vhd
+    src/vhdl/mms_dp_split.vhd
+    src/vhdl/dp_pad_insert.vhd
+    src/vhdl/dp_pad_remove.vhd
+    src/vhdl/dp_block_gen.vhd
+    src/vhdl/dp_bsn_source.vhd
+    src/vhdl/dp_bsn_source_reg.vhd
+    src/vhdl/mms_dp_bsn_source.vhd
+    src/vhdl/dp_bsn_scheduler.vhd
+    src/vhdl/dp_bsn_scheduler_reg.vhd
+    src/vhdl/mms_dp_bsn_scheduler.vhd
+    src/vhdl/dp_bsn_delay.vhd
+    src/vhdl/dp_bsn_align.vhd
+    src/vhdl/dp_frame_rd.vhd
+    src/vhdl/dp_frame_fsn.vhd
+    src/vhdl/dp_frame_tx.vhd
+    src/vhdl/dp_frame_rx.vhd
+    src/vhdl/dp_frame_status.vhd
+    src/vhdl/dp_frame.vhd
+    src/vhdl/dp_unframe.vhd
+    src/vhdl/dp_repack.vhd
+    src/vhdl/dp_frame_repack.vhd
+    src/vhdl/dp_frame_scheduler.vhd
+    src/vhdl/dp_packet_enc.vhd
+    src/vhdl/dp_packet_enc_channel_lo.vhd
+    src/vhdl/dp_packet_dec.vhd
+    src/vhdl/dp_packet_dec_channel_lo.vhd
+    src/vhdl/dp_gap.vhd
+    src/vhdl/dp_mon.vhd
+    src/vhdl/dp_bsn_monitor.vhd
+    src/vhdl/dp_bsn_monitor_reg.vhd
+    src/vhdl/mms_dp_bsn_monitor.vhd
+    src/vhdl/dp_distribute.vhd
+    src/vhdl/dp_ram_from_mm.vhd
+    src/vhdl/dp_ram_from_mm_reg.vhd
+    src/vhdl/mms_dp_ram_from_mm.vhd
+    src/vhdl/dp_ram_to_mm.vhd
+    src/vhdl/dp_hdr_insert.vhd
+    src/vhdl/dp_hdr_remove.vhd
+    src/vhdl/dp_tail_remove.vhd
+    src/vhdl/dp_frame_remove.vhd
+    src/vhdl/dp_throttle.vhd
+    src/vhdl/dp_throttle_reg.vhd
+    src/vhdl/mms_dp_throttle.vhd
+    src/vhdl/dp_packet_merge.vhd
+    src/vhdl/mms_dp_packet_merge.vhd
+    src/vhdl/dp_packet_unmerge.vhd
+    src/vhdl/dp_dummy_source.vhd
+    src/vhdl/dp_field_blk.vhd
+    src/vhdl/dp_offload_tx.vhd
+    src/vhdl/dp_offload_tx_len_calc.vhd
+    src/vhdl/dp_offload_tx_dev.vhd
+    src/vhdl/dp_offload_rx.vhd
+    src/vhdl/dp_offload_rx_dev.vhd
+    src/vhdl/dp_deinterleave.vhd
+    src/vhdl/dp_reinterleave.vhd
+    src/vhdl/dp_requantize.vhd
+    src/vhdl/dp_wideband_sp_arr_scope.vhd
+    src/vhdl/dp_wideband_wb_arr_scope.vhd
+    src/vhdl/dp_throttle_sop.vhd
+    src/vhdl/dp_barrel_shift.vhd
+    src/vhdl/dp_shiftram.vhd
+    
+    tb/vhdl/dp_stream_player.vhd
+    tb/vhdl/dp_stream_recorder.vhd
+    tb/vhdl/dp_stream_rec_play.vhd
+    
+    build/synth/quartus/dp_top.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_dp_pkg.vhd
+    
+    tb/vhdl/dp_phy_link.vhd
+    
+    tb/vhdl/tb_dp_block_gen.vhd
+    tb/vhdl/tb_dp_bsn_align.vhd
+    tb/vhdl/tb_dp_bsn_monitor.vhd
+    tb/vhdl/tb_dp_bsn_source.vhd
+    tb/vhdl/tb_dp_demux.vhd
+    tb/vhdl/tb2_dp_demux.vhd
+    tb/vhdl/tb3_dp_demux.vhd
+    tb/vhdl/tb_dp_concat.vhd
+    tb/vhdl/tb_dp_deinterleave.vhd
+    tb/vhdl/tb_dp_distribute.vhd
+    tb/vhdl/tb_dp_fifo_fill.vhd
+    tb/vhdl/tb_dp_fifo_info.vhd
+    tb/vhdl/tb_dp_fifo_dc.vhd
+    tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
+    tb/vhdl/tb_dp_fifo_sc.vhd
+    tb/vhdl/tb_dp_fifo_to_mm.vhd
+    tb/vhdl/tb_dp_flush.vhd
+    tb/vhdl/tb_dp_gap.vhd
+    tb/vhdl/tb_dp_hdr_insert_remove.vhd
+    tb/vhdl/tb_dp_frame_rd.vhd
+    tb/vhdl/tb_dp_frame_scheduler.vhd
+    tb/vhdl/tb_dp_latency_adapter.vhd
+    tb/vhdl/tb_dp_mux.vhd
+    tb/vhdl/tb2_dp_mux.vhd
+    tb/vhdl/tb3_dp_mux.vhd
+    tb/vhdl/tb_dp_packet.vhd
+    tb/vhdl/tb_dp_packet_merge.vhd
+    tb/vhdl/tb_dp_packetizing.vhd
+    tb/vhdl/tb_dp_pad_insert_remove.vhd
+    tb/vhdl/tb_dp_pipeline.vhd
+    tb/vhdl/tb_dp_pipeline_ready.vhd
+    tb/vhdl/tb_dp_reinterleave.vhd
+    tb/vhdl/tb_dp_shiftreg.vhd
+    tb/vhdl/tb_dp_split.vhd
+    tb/vhdl/tb_dp_tail_remove.vhd
+    tb/vhdl/tb_dp_throttle_sop.vhd
+    tb/vhdl/tb_mms_dp_fields.vhd
+    
+    tb/vhdl/tb_tb_dp_block_gen.vhd
+    tb/vhdl/tb_tb_dp_bsn_align.vhd
+    tb/vhdl/tb_tb_dp_concat.vhd
+    tb/vhdl/tb_tb_dp_demux.vhd
+    tb/vhdl/tb_tb2_dp_demux.vhd
+    tb/vhdl/tb_tb3_dp_demux.vhd
+    tb/vhdl/tb_tb_dp_distribute.vhd
+    tb/vhdl/tb_tb_dp_flush.vhd
+    tb/vhdl/tb_tb_dp_fifo_info.vhd
+    tb/vhdl/tb_tb_dp_fifo_sc.vhd
+    tb/vhdl/tb_tb_dp_fifo_fill.vhd
+    tb/vhdl/tb_tb_dp_fifo_dc.vhd
+    tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
+    tb/vhdl/tb_tb_dp_frame_scheduler.vhd
+    tb/vhdl/tb_tb_dp_mux.vhd
+    tb/vhdl/tb_tb2_dp_mux.vhd
+    tb/vhdl/tb_tb3_dp_mux.vhd
+    tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
+    tb/vhdl/tb_tb_dp_packetizing.vhd
+    tb/vhdl/tb_tb_dp_packet.vhd
+    tb/vhdl/tb_tb_dp_packet_merge.vhd
+    tb/vhdl/tb_tb_dp_pipeline.vhd
+    tb/vhdl/tb_tb_dp_pipeline_ready.vhd
+    tb/vhdl/tb_tb_dp_split.vhd
+    
+    tb/vhdl/tb_tb_tb_dp_backpressure.vhd

libraries/base/uth/hdllib.cfg

+hdl_lib_name = uth
+hdl_library_clause_name = uth_lib
+hdl_lib_uses = common dp easics
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    src/vhdl/uth_pkg.vhd
+    src/vhdl/uth_tx.vhd
+    src/vhdl/uth_rx_tlen.vhd
+    src/vhdl/uth_rx.vhd
+    src/vhdl/uth_terminal_tx.vhd
+    src/vhdl/uth_terminal_rx.vhd
+    src/vhdl/uth_terminal_bidir.vhd
+
+test_bench_files = 
+    tb/vhdl/tb_uth.vhd
+    tb/vhdl/tb_uth_dp_packet.vhd
+    tb/vhdl/tb_uth_terminals.vhd
+    tb/vhdl/tb_tb_uth.vhd
+    tb/vhdl/tb_tb_uth_dp_packet.vhd
+    tb/vhdl/tb_tb_uth_terminals.vhd
+    tb/vhdl/tb_tb_tb_uth_regression.vhd

libraries/io/i2c/hdllib.cfg

+hdl_lib_name = i2c
+hdl_library_clause_name = i2c_lib
+hdl_lib_uses = common
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    src/vhdl/i2c_pkg.vhd
+    src/vhdl/i2c_bit.vhd
+    src/vhdl/i2c_byte.vhd
+    src/vhdl/i2c_smbus_pkg.vhd
+    src/vhdl/i2c_smbus.vhd
+    src/vhdl/i2c_list_ctrl.vhd
+    src/vhdl/i2c_commander_pkg.vhd
+    src/vhdl/i2c_dev_max1617_pkg.vhd
+    src/vhdl/i2c_dev_max6652_pkg.vhd
+    src/vhdl/i2c_dev_ltc4260_pkg.vhd
+    src/vhdl/i2c_dev_unb_pkg.vhd
+    src/vhdl/i2c_dev_adu_pkg.vhd
+    src/vhdl/i2c_commander_aduh_pkg.vhd
+    src/vhdl/i2c_commander_unbh_pkg.vhd
+    src/vhdl/i2c_commander_reg.vhd
+    src/vhdl/i2c_commander_ctrl.vhd
+    src/vhdl/i2c_commander.vhd
+    src/vhdl/i2c_mm.vhd
+    src/vhdl/i2c_master.vhd
+    src/vhdl/avs_i2c_master.vhd
+
+test_bench_files = 
+    tb/vhdl/i2c_slv_device.vhd
+    src/vhdl/i2cslave.vhd
+    tb/vhdl/dev_pca9555.vhd
+    tb/vhdl/dev_max1618.vhd
+    tb/vhdl/dev_max6652.vhd
+    tb/vhdl/dev_ltc4260.vhd
+    tb/vhdl/tb_i2cslave.vhd
+    tb/vhdl/tb_i2c_master.vhd
+    tb/vhdl/tb_avs_i2c_master.vhd
+    tb/vhdl/tb_i2c_commander.vhd

libraries/io/ppsh/hdllib.cfg

+hdl_lib_name = ppsh
+hdl_library_clause_name = ppsh_lib
+hdl_lib_uses = common
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    src/vhdl/ppsh.vhd
+    src/vhdl/mm_ppsh.vhd
+    src/vhdl/ppsh_reg.vhd
+    src/vhdl/mms_ppsh.vhd
+    
+test_bench_files =
+    tb/vhdl/tb_ppsh.vhd
+    tb/vhdl/tb_mms_ppsh.vhd