-Added hdllib.cfg.

applications/apertif/designs/apertif_unb1_fn_bf_emu/hdllib.cfg

+hdl_lib_name = apertif_unb1_fn_bf_emu
+hdl_library_clause_name = apertif_unb1_fn_bf_emu_lib
+hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif tech_ddr io_ddr
+hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master 
+                   ip_stratixiv_ddr3_uphy_4g_800_slave
+                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+
+synth_top_level_entity =
+
+synth_files =     
+    $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_bf_emu/sopc_apertif_unb1_fn_bf_emu.vhd    
+    ../apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_bf_emu_udp_offload.vhd
+    src/vhdl/mmm_apertif_unb1_fn_bf_emu.vhd
+    src/vhdl/apertif_unb1_fn_bf_emu.vhd
+    
+test_bench_files =                                                                      
+    tb_apertif_unb1_fn_bf_emu.vhd                                       
+
+modelsim_copy_files = ../../src/hex hex                                                   
+
+quartus_copy_files = ../../quartus/sopc_apertif_unb1_fn_bf_emu.sopc .
+
+quartus_qsf_files =                                                       
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+    apertif_unb1_fn_bf_emu_base_pins.tcl
+    ../../quartus/apertif_unb1_bf_constraints.tcl
+    
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_bf_emu/sopc_apertif_unb1_fn_bf_emu.qip
+
+modelsim_search_libraries =                                                                                            
+    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+    altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip    
+