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RTSD
HDL
Commits
79459fd8
Commit
79459fd8
authored
1 year ago
by
David Brouwer
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!363
Porting ram for Intel Agilex 7
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libraries/technology/ip_agi027_xxxx/fifo/README.txt
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79459fd8
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@@ -29,7 +29,7 @@ Contents:
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@@ -29,7 +29,7 @@ Contents:
terminal command generate_ip_libs <buildset> and finish to save the changes.
terminal command generate_ip_libs <buildset> and finish to save the changes.
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
necessary to make it work.
necessary to make it work.
. git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original i
f
case it needs to be modified.
. git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original i
n
case it needs to be modified.
- methode B:
- methode B:
. copy original ip_arria_e2sg_<fifo_name>.vhd file.
. copy original ip_arria_e2sg_<fifo_name>.vhd file.
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@@ -42,7 +42,7 @@ Contents:
...
@@ -42,7 +42,7 @@ Contents:
directory using the terminal command generate_ip_libs <buildset> to finish it.
directory using the terminal command generate_ip_libs <buildset> to finish it.
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
necessary to make it work.
necessary to make it work.
. git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original i
f
case it needs to be modified.
. git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original i
n
case it needs to be modified.
this yields:
this yields:
...
@@ -82,7 +82,7 @@ Contents:
...
@@ -82,7 +82,7 @@ Contents:
set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_xxxx/fifo/quartus/fifo.qsf could be added to the hdllib.cfg under
quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_xxxx/fifo/quartus/fifo.qsf could be added to the hdllib.cfg under
[quartus_project_file]. Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
[quartus_project_file]. Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
The Quartus project ip_agi027_xxxx_fif.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_xxxx_fifo/ was used to verify that the FIFO IP
The Quartus project ip_agi027_xxxx_fif
o
.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_xxxx_fifo/ was used to verify that the FIFO IP
actually synthesise to the appropriate FPGA resources. Use the Quartus GUI to manually select a top level component for synthesis e.g.
actually synthesise to the appropriate FPGA resources. Use the Quartus GUI to manually select a top level component for synthesis e.g.
by right clicking the entity vhd file in the file tab of the Quartus project navigator window. For the (default) testcondition the
by right clicking the entity vhd file in the file tab of the Quartus project navigator window. For the (default) testcondition the
generics are set to 1024 words deep and 20 bits wide. Then check the resource usage in the synthesis and fitter reports.
generics are set to 1024 words deep and 20 bits wide. Then check the resource usage in the synthesis and fitter reports.
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