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Commit 78ec618a authored by Dumez's avatar Dumez
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Add eth Stats and stp for monitoring

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applications/rfidb/designs/rfidb/doc/structure.dia 0 → 100644
+ 0
− 0
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File added
applications/rfidb/designs/rfidb/hdllib.cfg
+ 5
− 1
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hdl_lib_name = unb1_rfidb hdl_lib_name = unb1_rfidb
hdl_library_clause_name = unb1_rfidb_lib hdl_library_clause_name = unb1_rfidb_lib
hdl_lib_uses_synth = common dp unb1_board eth detector tech_tse hdl_lib_uses_synth = common dp unb1_board diag eth detector tech_tse
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
...@@ -10,6 +10,10 @@ synth_top_level_entity = ...@@ -10,6 +10,10 @@ synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
quartus/qsys_unb1_rfidb.qsys . quartus/qsys_unb1_rfidb.qsys .
quartus/stp32.stp quartus/stp32.stp
$RADIOHDL/libraries/base/dp/designs/unb1_dp_offload/src/hex hex
modelsim_copy_files =
$RADIOHDL/libraries/base/dp/designs/unb1_dp_offload/src/hex hex
synth_files = synth_files =
src/vhdl/stp32.vhd src/vhdl/stp32.vhd
......
applications/rfidb/designs/rfidb/src/vhdl/mmm_unb1_rfidb.vhd
+ 179
− 36
View file @ 78ec618a
...@@ -38,6 +38,7 @@ ENTITY mmm_unb1_rfidb IS ...@@ -38,6 +38,7 @@ ENTITY mmm_unb1_rfidb IS
g_sim_unb_nr : NATURAL := 0; g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; g_sim_node_nr : NATURAL := 0;
g_use_qsys : BOOLEAN := FALSE; g_use_qsys : BOOLEAN := FALSE;
g_bg_block_size : NATURAL;
g_hdr_field_arr : t_common_field_arr g_hdr_field_arr : t_common_field_arr
); );
PORT ( PORT (
...@@ -103,17 +104,51 @@ ENTITY mmm_unb1_rfidb IS ...@@ -103,17 +104,51 @@ ENTITY mmm_unb1_rfidb IS
reg_remu_miso : IN t_mem_miso; reg_remu_miso : IN t_mem_miso;
-- BEAM0_eth -- BEAM0_eth
Beam0_eth_tse_mosi : OUT t_mem_mosi; beam0_eth_tse_mosi : OUT t_mem_mosi;
Beam0_eth_tse_miso : IN t_mem_miso; beam0_eth_tse_miso : IN t_mem_miso;
Beam0_eth_reg_mosi : OUT t_mem_mosi; beam0_eth_reg_mosi : OUT t_mem_mosi;
Beam0_eth_reg_miso : IN t_mem_miso; beam0_eth_reg_miso : IN t_mem_miso;
Beam0_eth_reg_interrupt : IN STD_LOGIC; beam0_eth_reg_interrupt : IN STD_LOGIC;
Beam0_eth_ram_mosi : OUT t_mem_mosi; beam0_eth_ram_mosi : OUT t_mem_mosi;
Beam0_eth_ram_miso : IN t_mem_miso; beam0_eth_ram_miso : IN t_mem_miso;
-- BEAM0_offload -- BEAM0_offload
Beam0_dp_offload_rx_reg_hdr_dat_mosi : OUT t_mem_mosi; beam0_dp_offload_rx_reg_hdr_dat_mosi : OUT t_mem_mosi;
Beam0_dp_offload_rx_reg_hdr_dat_miso : IN t_mem_miso beam0_dp_offload_rx_reg_hdr_dat_miso : IN t_mem_miso;
-- BEAM1_eth
beam1_eth_tse_mosi : OUT t_mem_mosi;
beam1_eth_tse_miso : IN t_mem_miso;
beam1_eth_reg_mosi : OUT t_mem_mosi;
beam1_eth_reg_miso : IN t_mem_miso;
beam1_eth_reg_interrupt : IN STD_LOGIC;
beam1_eth_ram_mosi : OUT t_mem_mosi;
beam1_eth_ram_miso : IN t_mem_miso;
-- BEAM1_offload
beam1_dp_offload_rx_reg_hdr_dat_mosi : OUT t_mem_mosi;
beam1_dp_offload_rx_reg_hdr_dat_miso : IN t_mem_miso;
-- stats_eth
stats_eth_tse_mosi : OUT t_mem_mosi;
stats_eth_tse_miso : IN t_mem_miso;
stats_eth_reg_mosi : OUT t_mem_mosi;
stats_eth_reg_miso : IN t_mem_miso;
stats_eth_reg_interrupt : IN STD_LOGIC;
stats_eth_ram_mosi : OUT t_mem_mosi;
stats_eth_ram_miso : IN t_mem_miso;
-- stats_offload
stats_dp_offload_rx_reg_hdr_dat_mosi : OUT t_mem_mosi;
stats_dp_offload_rx_reg_hdr_dat_miso : IN t_mem_miso;
stats_dp_offload_tx_reg_hdr_dat_mosi : OUT t_mem_mosi;
stats_dp_offload_tx_reg_hdr_dat_miso : IN t_mem_miso;
-- stats block generator
ram_diag_bg_mosi : OUT t_mem_mosi;
ram_diag_bg_miso : IN t_mem_miso;
reg_diag_bg_mosi : OUT t_mem_mosi;
reg_diag_bg_miso : IN t_mem_miso
); );
END mmm_unb1_rfidb; END mmm_unb1_rfidb;
...@@ -154,6 +189,10 @@ ARCHITECTURE str OF mmm_unb1_rfidb IS ...@@ -154,6 +189,10 @@ ARCHITECTURE str OF mmm_unb1_rfidb IS
CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(c_beam_nof_streams* pow2(c_reg_dp_offload_rx_hdr_dat_adr_w)); CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(c_beam_nof_streams* pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
-- Block generator
CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(pow2(ceil_log2(g_bg_block_size)));
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- mm_file component -- mm_file component
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
...@@ -210,6 +249,26 @@ BEGIN ...@@ -210,6 +249,26 @@ BEGIN
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG") u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso ); PORT MAP(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
-- beam0
u_mm_file_reg_Beam0_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "BEAM0_ETH_MMS_REG")
PORT MAP(mm_rst, i_mm_clk, Beam0_eth_reg_mosi, Beam0_eth_reg_miso );
u_mm_file_tse_Beam0_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "BEAM0_ETH_MMS_TSE")
PORT MAP(mm_rst, i_mm_clk, Beam0_eth_tse_mosi, Beam0_eth_tse_miso );
u_mm_file_ram_Beam0_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "BEAM0_ETH_MMS_RAM")
PORT MAP(mm_rst, i_mm_clk, Beam0_eth_ram_mosi, Beam0_eth_ram_miso );
u_mm_file_reg_Beam0_dp_offload_rx_reg_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BEAM0_DP_OFFLOAD_RX_HDR_DAT")
PORT MAP(mm_rst, i_mm_clk, beam0_dp_offload_rx_reg_hdr_dat_mosi, beam0_dp_offload_rx_reg_hdr_dat_miso );
-- beam1
-- stats
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BLOCK_GEN")
PORT MAP(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BLOCK_GEN")
PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get -- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns -- the simulation time in ns
...@@ -226,7 +285,7 @@ BEGIN ...@@ -226,7 +285,7 @@ BEGIN
PORT MAP ( PORT MAP (
clk_0 => xo_clk, clk_0 => xo_clk,
reset_n => xo_rst_n, reset_n => xo_rst_n,
mm_clk => i_mm_clk, mm_clk_clk => i_mm_clk,
tse_clk => i_eth1g_tse_clk, tse_clk => i_eth1g_tse_clk,
epcs_clk => i_epcs_clk, epcs_clk => i_epcs_clk,
cal_rec_clk => i_cal_rec_clk, cal_rec_clk => i_cal_rec_clk,
...@@ -361,32 +420,116 @@ BEGIN ...@@ -361,32 +420,116 @@ BEGIN
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0), coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- BEAM0_eth -- BEAM0_eth
beam0_eth_tse_address_export => BEAM0_eth_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0), beam0_eth_clk_export => open,
beam0_eth_tse_write_export => BEAM0_eth_tse_mosi.wr, beam0_eth_reset_export => open,
beam0_eth_tse_writedata_export => BEAM0_eth_tse_mosi.wrdata(c_word_w-1 DOWNTO 0), beam0_eth_tse_address_export => beam0_eth_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
beam0_eth_tse_read_export => BEAM0_eth_tse_mosi.rd, beam0_eth_tse_write_export => beam0_eth_tse_mosi.wr,
beam0_eth_tse_readdata_export => BEAM0_eth_tse_miso.rddata(c_word_w-1 DOWNTO 0), beam0_eth_tse_writedata_export => beam0_eth_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
beam0_eth_tse_waitrequest_export => BEAM0_eth_tse_miso.waitrequest, beam0_eth_tse_read_export => beam0_eth_tse_mosi.rd,
beam0_eth_reg_address_export => BEAM0_eth_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0), beam0_eth_tse_readdata_export => beam0_eth_tse_miso.rddata(c_word_w-1 DOWNTO 0),
beam0_eth_reg_write_export => BEAM0_eth_reg_mosi.wr, beam0_eth_tse_waitrequest_export => beam0_eth_tse_miso.waitrequest,
beam0_eth_reg_writedata_export => BEAM0_eth_reg_mosi.wrdata(c_word_w-1 DOWNTO 0), beam0_eth_reg_address_export => beam0_eth_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
beam0_eth_reg_read_export => BEAM0_eth_reg_mosi.rd, beam0_eth_reg_write_export => beam0_eth_reg_mosi.wr,
beam0_eth_reg_readdata_export => BEAM0_eth_reg_miso.rddata(c_word_w-1 DOWNTO 0), beam0_eth_reg_writedata_export => beam0_eth_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
beam0_eth_ram_address_export => BEAM0_eth_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0), beam0_eth_reg_read_export => beam0_eth_reg_mosi.rd,
beam0_eth_ram_write_export => BEAM0_eth_ram_mosi.wr, beam0_eth_reg_readdata_export => beam0_eth_reg_miso.rddata(c_word_w-1 DOWNTO 0),
beam0_eth_ram_writedata_export => BEAM0_eth_ram_mosi.wrdata(c_word_w-1 DOWNTO 0), beam0_eth_ram_address_export => beam0_eth_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
beam0_eth_ram_read_export => BEAM0_eth_ram_mosi.rd, beam0_eth_ram_write_export => beam0_eth_ram_mosi.wr,
beam0_eth_ram_readdata_export => BEAM0_eth_ram_miso.rddata(c_word_w-1 DOWNTO 0), beam0_eth_ram_writedata_export => beam0_eth_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
beam0_eth_ram_read_export => beam0_eth_ram_mosi.rd,
beam0_eth_ram_readdata_export => beam0_eth_ram_miso.rddata(c_word_w-1 DOWNTO 0),
beam0_eth_irq_export => open, beam0_eth_irq_export => open,
Beam0_dp_offload_rx_reg_hdr_dat_reset_export => open, beam0_dp_offload_rx_reg_hdr_dat_reset_export => open,
Beam0_dp_offload_rx_reg_hdr_dat_clk_export => open, beam0_dp_offload_rx_reg_hdr_dat_clk_export => open,
Beam0_dp_offload_rx_reg_hdr_dat_address_export => Beam0_dp_offload_rx_reg_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0), beam0_dp_offload_rx_reg_hdr_dat_address_export => beam0_dp_offload_rx_reg_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
Beam0_dp_offload_rx_reg_hdr_dat_write_export => Beam0_dp_offload_rx_reg_hdr_dat_mosi.wr, beam0_dp_offload_rx_reg_hdr_dat_write_export => beam0_dp_offload_rx_reg_hdr_dat_mosi.wr,
Beam0_dp_offload_rx_reg_hdr_dat_writedata_export => Beam0_dp_offload_rx_reg_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0), beam0_dp_offload_rx_reg_hdr_dat_writedata_export => beam0_dp_offload_rx_reg_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
Beam0_dp_offload_rx_reg_hdr_dat_read_export => Beam0_dp_offload_rx_reg_hdr_dat_mosi.rd, beam0_dp_offload_rx_reg_hdr_dat_read_export => beam0_dp_offload_rx_reg_hdr_dat_mosi.rd,
Beam0_dp_offload_rx_reg_hdr_dat_readdata_export => Beam0_dp_offload_rx_reg_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0) beam0_dp_offload_rx_reg_hdr_dat_readdata_export => beam0_dp_offload_rx_reg_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
-- BEAM1_eth
beam1_eth_clk_export => open,
beam1_eth_reset_export => open,
beam1_eth_tse_address_export => beam1_eth_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
beam1_eth_tse_write_export => beam1_eth_tse_mosi.wr,
beam1_eth_tse_writedata_export => beam1_eth_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
beam1_eth_tse_read_export => beam1_eth_tse_mosi.rd,
beam1_eth_tse_readdata_export => beam1_eth_tse_miso.rddata(c_word_w-1 DOWNTO 0),
beam1_eth_tse_waitrequest_export => beam1_eth_tse_miso.waitrequest,
beam1_eth_reg_address_export => beam1_eth_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
beam1_eth_reg_write_export => beam1_eth_reg_mosi.wr,
beam1_eth_reg_writedata_export => beam1_eth_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
beam1_eth_reg_read_export => beam1_eth_reg_mosi.rd,
beam1_eth_reg_readdata_export => beam1_eth_reg_miso.rddata(c_word_w-1 DOWNTO 0),
beam1_eth_ram_address_export => beam1_eth_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
beam1_eth_ram_write_export => beam1_eth_ram_mosi.wr,
beam1_eth_ram_writedata_export => beam1_eth_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
beam1_eth_ram_read_export => beam1_eth_ram_mosi.rd,
beam1_eth_ram_readdata_export => beam1_eth_ram_miso.rddata(c_word_w-1 DOWNTO 0),
beam1_eth_irq_export => open,
beam1_dp_offload_rx_reg_hdr_dat_reset_export => open,
beam1_dp_offload_rx_reg_hdr_dat_clk_export => open,
beam1_dp_offload_rx_reg_hdr_dat_address_export => beam1_dp_offload_rx_reg_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
beam1_dp_offload_rx_reg_hdr_dat_write_export => beam1_dp_offload_rx_reg_hdr_dat_mosi.wr,
beam1_dp_offload_rx_reg_hdr_dat_writedata_export => beam1_dp_offload_rx_reg_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
beam1_dp_offload_rx_reg_hdr_dat_read_export => beam1_dp_offload_rx_reg_hdr_dat_mosi.rd,
beam1_dp_offload_rx_reg_hdr_dat_readdata_export => beam1_dp_offload_rx_reg_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
-- stats_eth
stats_eth_clk_export => open,
stats_eth_reset_export => open,
stats_eth_tse_address_export => stats_eth_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
stats_eth_tse_write_export => stats_eth_tse_mosi.wr,
stats_eth_tse_writedata_export => stats_eth_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
stats_eth_tse_read_export => stats_eth_tse_mosi.rd,
stats_eth_tse_readdata_export => stats_eth_tse_miso.rddata(c_word_w-1 DOWNTO 0),
stats_eth_tse_waitrequest_export => stats_eth_tse_miso.waitrequest,
stats_eth_reg_address_export => stats_eth_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
stats_eth_reg_write_export => stats_eth_reg_mosi.wr,
stats_eth_reg_writedata_export => stats_eth_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
stats_eth_reg_read_export => stats_eth_reg_mosi.rd,
stats_eth_reg_readdata_export => stats_eth_reg_miso.rddata(c_word_w-1 DOWNTO 0),
stats_eth_ram_address_export => stats_eth_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
stats_eth_ram_write_export => stats_eth_ram_mosi.wr,
stats_eth_ram_writedata_export => stats_eth_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
stats_eth_ram_read_export => stats_eth_ram_mosi.rd,
stats_eth_ram_readdata_export => stats_eth_ram_miso.rddata(c_word_w-1 DOWNTO 0),
stats_eth_irq_export => open,
stats_dp_offload_rx_reg_hdr_dat_reset_export => open,
stats_dp_offload_rx_reg_hdr_dat_clk_export => open,
stats_dp_offload_rx_reg_hdr_dat_address_export => stats_dp_offload_rx_reg_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
stats_dp_offload_rx_reg_hdr_dat_write_export => stats_dp_offload_rx_reg_hdr_dat_mosi.wr,
stats_dp_offload_rx_reg_hdr_dat_writedata_export => stats_dp_offload_rx_reg_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
stats_dp_offload_rx_reg_hdr_dat_read_export => stats_dp_offload_rx_reg_hdr_dat_mosi.rd,
stats_dp_offload_rx_reg_hdr_dat_readdata_export => stats_dp_offload_rx_reg_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
stats_dp_offload_tx_reg_hdr_dat_reset_export => open,
stats_dp_offload_tx_reg_hdr_dat_clk_export => open,
stats_dp_offload_tx_reg_hdr_dat_address_export => stats_dp_offload_tx_reg_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
stats_dp_offload_tx_reg_hdr_dat_write_export => stats_dp_offload_tx_reg_hdr_dat_mosi.wr,
stats_dp_offload_tx_reg_hdr_dat_writedata_export => stats_dp_offload_tx_reg_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
stats_dp_offload_tx_reg_hdr_dat_read_export => stats_dp_offload_tx_reg_hdr_dat_mosi.rd,
stats_dp_offload_tx_reg_hdr_dat_readdata_export => stats_dp_offload_tx_reg_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
-- diag_block_gen
reg_diag_block_gen_clk_export => OPEN,
reg_diag_block_gen_reset_export => OPEN,
reg_diag_block_gen_address_export => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
reg_diag_block_gen_write_export => reg_diag_bg_mosi.wr,
reg_diag_block_gen_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_block_gen_read_export => reg_diag_bg_mosi.rd,
reg_diag_block_gen_readdata_export => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_block_gen_clk_export => OPEN,
ram_diag_block_gen_reset_export => OPEN,
ram_diag_block_gen_address_export => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w-1 DOWNTO 0),
ram_diag_block_gen_write_export => ram_diag_bg_mosi.wr,
ram_diag_block_gen_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_block_gen_read_export => ram_diag_bg_mosi.rd,
ram_diag_block_gen_readdata_export => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0)
); );
END GENERATE; END GENERATE;
......
applications/rfidb/designs/rfidb/src/vhdl/qsys_unb1_rfidb_pkg.vhd
+ 83
− 8
View file @ 78ec618a
...@@ -32,9 +32,8 @@ PACKAGE qsys_unb1_rfidb_pkg IS ...@@ -32,9 +32,8 @@ PACKAGE qsys_unb1_rfidb_pkg IS
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
mm_clk : out std_logic; -- clk
coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export coe_address_export_from_the_pio_pps : out std_logic; -- export
coe_reset_export_from_the_pio_pps : out std_logic; -- export coe_reset_export_from_the_pio_pps : out std_logic; -- export
coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
...@@ -44,7 +43,7 @@ PACKAGE qsys_unb1_rfidb_pkg IS ...@@ -44,7 +43,7 @@ PACKAGE qsys_unb1_rfidb_pkg IS
coe_reset_export_from_the_reg_wdi : out std_logic; -- export coe_reset_export_from_the_reg_wdi : out std_logic; -- export
coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
coe_address_export_from_the_reg_dpmm_ctrl : out std_logic;--_vector(0 downto 0); -- export coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
coe_clk_export_from_the_rom_system_info : out std_logic; -- export coe_clk_export_from_the_rom_system_info : out std_logic; -- export
coe_reset_export_from_the_reg_remu : out std_logic; -- export coe_reset_export_from_the_reg_remu : out std_logic; -- export
coe_read_export_from_the_reg_unb_sens : out std_logic; -- export coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
...@@ -64,9 +63,9 @@ PACKAGE qsys_unb1_rfidb_pkg IS ...@@ -64,9 +63,9 @@ PACKAGE qsys_unb1_rfidb_pkg IS
coe_clk_export_from_the_pio_pps : out std_logic; -- export coe_clk_export_from_the_pio_pps : out std_logic; -- export
coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
coe_address_export_from_the_reg_dpmm_data : out std_logic;--_vector(0 downto 0); -- export coe_address_export_from_the_reg_dpmm_data : out std_logic; -- export
coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export coe_address_export_from_the_reg_wdi : out std_logic; -- export
coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
coe_write_export_from_the_pio_system_info : out std_logic; -- export coe_write_export_from_the_pio_system_info : out std_logic; -- export
coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
...@@ -88,6 +87,7 @@ PACKAGE qsys_unb1_rfidb_pkg IS ...@@ -88,6 +87,7 @@ PACKAGE qsys_unb1_rfidb_pkg IS
coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
tse_clk : out std_logic; -- clk tse_clk : out std_logic; -- clk
epcs_clk : out std_logic; -- clk epcs_clk : out std_logic; -- clk
mm_clk_clk : out std_logic; -- clk
coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
...@@ -107,7 +107,7 @@ PACKAGE qsys_unb1_rfidb_pkg IS ...@@ -107,7 +107,7 @@ PACKAGE qsys_unb1_rfidb_pkg IS
coe_clk_export_from_the_reg_remu : out std_logic; -- export coe_clk_export_from_the_reg_remu : out std_logic; -- export
coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
coe_address_export_from_the_reg_mmdp_ctrl : out std_logic;--_vector(0 downto 0); -- export coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
coe_write_export_from_the_reg_epcs : out std_logic; -- export coe_write_export_from_the_reg_epcs : out std_logic; -- export
coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
...@@ -122,7 +122,7 @@ PACKAGE qsys_unb1_rfidb_pkg IS ...@@ -122,7 +122,7 @@ PACKAGE qsys_unb1_rfidb_pkg IS
coe_reset_export_from_the_rom_system_info : out std_logic; -- export coe_reset_export_from_the_rom_system_info : out std_logic; -- export
coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
coe_address_export_from_the_reg_mmdp_data : out std_logic;--_vector(0 downto 0); -- export coe_address_export_from_the_reg_mmdp_data : out std_logic; -- export
coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
...@@ -165,7 +165,82 @@ PACKAGE qsys_unb1_rfidb_pkg IS ...@@ -165,7 +165,82 @@ PACKAGE qsys_unb1_rfidb_pkg IS
beam0_eth_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export beam0_eth_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
beam0_eth_irq_export : in std_logic := 'X'; -- export beam0_eth_irq_export : in std_logic := 'X'; -- export
beam0_eth_reg_writedata_export : out std_logic_vector(31 downto 0); -- export beam0_eth_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
cal_rec_clk : out std_logic -- clk cal_rec_clk : out std_logic; -- clk
beam0_eth_clk_export : out std_logic; -- export
beam0_eth_reset_export : out std_logic; -- export
beam1_eth_reset_export : out std_logic; -- export
beam1_eth_clk_export : out std_logic; -- export
beam1_eth_tse_write_export : out std_logic; -- export
beam1_eth_tse_read_export : out std_logic; -- export
beam1_eth_tse_address_export : out std_logic_vector(9 downto 0); -- export
beam1_eth_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
beam1_eth_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
beam1_eth_tse_waitrequest_export : in std_logic := 'X'; -- export
beam1_eth_reg_address_export : out std_logic_vector(3 downto 0); -- export
beam1_eth_reg_write_export : out std_logic; -- export
beam1_eth_reg_read_export : out std_logic; -- export
beam1_eth_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
beam1_eth_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
beam1_eth_ram_address_export : out std_logic_vector(9 downto 0); -- export
beam1_eth_ram_write_export : out std_logic; -- export
beam1_eth_ram_read_export : out std_logic; -- export
beam1_eth_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
beam1_eth_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
beam1_eth_irq_export : in std_logic := 'X'; -- export
beam1_dp_offload_rx_reg_hdr_dat_reset_export : out std_logic; -- export
beam1_dp_offload_rx_reg_hdr_dat_clk_export : out std_logic; -- export
beam1_dp_offload_rx_reg_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
beam1_dp_offload_rx_reg_hdr_dat_write_export : out std_logic; -- export
beam1_dp_offload_rx_reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
beam1_dp_offload_rx_reg_hdr_dat_read_export : out std_logic; -- export
beam1_dp_offload_rx_reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_block_gen_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_block_gen_read_export : out std_logic; -- export
ram_diag_block_gen_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_block_gen_write_export : out std_logic; -- export
ram_diag_block_gen_address_export : out std_logic_vector(9 downto 0); -- export
ram_diag_block_gen_clk_export : out std_logic; -- export
ram_diag_block_gen_reset_export : out std_logic; -- export
reg_diag_block_gen_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_block_gen_read_export : out std_logic; -- export
reg_diag_block_gen_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_block_gen_write_export : out std_logic; -- export
reg_diag_block_gen_address_export : out std_logic_vector(2 downto 0); -- export
reg_diag_block_gen_clk_export : out std_logic; -- export
reg_diag_block_gen_reset_export : out std_logic; -- export
stats_dp_offload_tx_reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
stats_dp_offload_tx_reg_hdr_dat_read_export : out std_logic; -- export
stats_dp_offload_tx_reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
stats_dp_offload_tx_reg_hdr_dat_write_export : out std_logic; -- export
stats_dp_offload_tx_reg_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
stats_dp_offload_tx_reg_hdr_dat_clk_export : out std_logic; -- export
stats_dp_offload_tx_reg_hdr_dat_reset_export : out std_logic; -- export
stats_dp_offload_rx_reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
stats_dp_offload_rx_reg_hdr_dat_read_export : out std_logic; -- export
stats_dp_offload_rx_reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
stats_dp_offload_rx_reg_hdr_dat_write_export : out std_logic; -- export
stats_dp_offload_rx_reg_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
stats_dp_offload_rx_reg_hdr_dat_clk_export : out std_logic; -- export
stats_dp_offload_rx_reg_hdr_dat_reset_export : out std_logic; -- export
stats_eth_irq_export : in std_logic := 'X'; -- export
stats_eth_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
stats_eth_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
stats_eth_ram_read_export : out std_logic; -- export
stats_eth_ram_write_export : out std_logic; -- export
stats_eth_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
stats_eth_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
stats_eth_reg_read_export : out std_logic; -- export
stats_eth_reg_write_export : out std_logic; -- export
stats_eth_reg_address_export : out std_logic_vector(3 downto 0); -- export
stats_eth_tse_waitrequest_export : in std_logic := 'X'; -- export
stats_eth_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
stats_eth_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
stats_eth_tse_read_export : out std_logic; -- export
stats_eth_tse_write_export : out std_logic; -- export
stats_eth_tse_address_export : out std_logic_vector(9 downto 0); -- export
stats_eth_clk_export : out std_logic; -- export
stats_eth_ram_address_export : out std_logic_vector(9 downto 0); -- export
stats_eth_reset_export : out std_logic -- export
); );
end component qsys_unb1_rfidb; end component qsys_unb1_rfidb;
......
applications/rfidb/designs/rfidb/src/vhdl/unb1_rfidb.vhd
+ 584
− 103
View file @ 78ec618a
This diff is collapsed.
applications/rfidb/designs/rfidb/tb/python/tc_unb1_rfidb.py
+ 49
− 8
View file @ 78ec618a
...@@ -183,11 +183,13 @@ def test_eth(tc,io,cmd): ...@@ -183,11 +183,13 @@ def test_eth(tc,io,cmd):
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd)) tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>') tc.append_log(3, '>>>')
eth = pi_eth.PiEth(tc, io) # eth = pi_eth.PiEth(tc, io)
# eth = pi_eth_OCB.PiEthOCB(tc, io, basename='AVS_ETH_0') eth = pi_eth_OCB.PiEthOCB(tc, io, basename='AVS_ETH_0')
# eth.ETH_read_setup() eth.ETH_read_setup()
# eth.PCS_read_setup() eth.PCS_read_setup()
# eth.MAC_read_setup() eth.MAC_read_setup()
tc.append_log(3, '')
tc.set_section_id('BeamB RAM buffer - ')
hdr = eth.read_hdr(0) hdr = eth.read_hdr(0)
eth.disassemble_hdr(hdr) eth.disassemble_hdr(hdr)
tc.append_log(3, '') tc.append_log(3, '')
...@@ -201,8 +203,7 @@ def conf_eth_BeamA(tc,io,cmd): ...@@ -201,8 +203,7 @@ def conf_eth_BeamA(tc,io,cmd):
tc.append_log(3, '>>>') tc.append_log(3, '>>>')
eth = pi_eth_OCB.PiEthOCB(tc, io, basename='BEAM0_ETH') eth = pi_eth_OCB.PiEthOCB(tc, io, basename='BEAM0_ETH')
eth.ETH_config(IP_ADDR=0x0A0B0050, MAC_ADDR=CommonBytes(0x01230A0B0150, c_eth_mac_addr_len), Demux=(4346,)) eth.ETH_config(IP_ADDR=0x0A0A0050, MAC_ADDR=CommonBytes(0x01230A0A0150, c_eth_mac_addr_len), Demux=(4346,))
# eth.ETH_config(IP_ADDR=0x0A0A0050, MAC_ADDR=CommonBytes(0x01230A0A0150, c_eth_mac_addr_len), Demux=(4346,))
eth.PCS_config() eth.PCS_config()
eth.MAC_config(MAC_ADDR=CommonBytes(0x01230A0B0150, c_eth_mac_addr_len), promisc=True) eth.MAC_config(MAC_ADDR=CommonBytes(0x01230A0B0150, c_eth_mac_addr_len), promisc=True)
...@@ -229,6 +230,9 @@ def test_eth_BeamA(tc,io,cmd): ...@@ -229,6 +230,9 @@ def test_eth_BeamA(tc,io,cmd):
def conf_eth_BeamB(tc,io,cmd): def conf_eth_BeamB(tc,io,cmd):
tc.append_log(1, '>>> BeamB not CONNECTED yet UNB1_RFIDB')
sys.exit(tc.get_result())
tc.set_section_id('BeamB configuration - ') tc.set_section_id('BeamB configuration - ')
tc.append_log(3, '>>>') tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd)) tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
...@@ -244,6 +248,9 @@ def conf_eth_BeamB(tc,io,cmd): ...@@ -244,6 +248,9 @@ def conf_eth_BeamB(tc,io,cmd):
def test_eth_BeamB(tc,io,cmd): def test_eth_BeamB(tc,io,cmd):
tc.append_log(1, '>>> >>> BeamB not CONNECTED yet UNB1_RFIDB')
sys.exit(tc.get_result())
tc.set_section_id('BeamB status - ') tc.set_section_id('BeamB status - ')
tc.append_log(3, '>>>') tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd)) tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
...@@ -260,6 +267,38 @@ def test_eth_BeamB(tc,io,cmd): ...@@ -260,6 +267,38 @@ def test_eth_BeamB(tc,io,cmd):
def conf_eth_Stats(tc,io,cmd):
tc.set_section_id('Stats configuration - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
eth = pi_eth_OCB.PiEthOCB(tc, io, basename='STATS_ETH')
eth.ETH_config(IP_ADDR=0x0A630009, MAC_ADDR=CommonBytes(0x00228608008, c_eth_mac_addr_len), Demux=(4346,))
eth.PCS_config()
eth.MAC_config(MAC_ADDR=CommonBytes(0x00228608008, c_eth_mac_addr_len), promisc=True)
tc.append_log(3, '')
def test_eth_Stats(tc,io,cmd):
tc.set_section_id('Stats status - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
eth = pi_eth_OCB.PiEthOCB(tc, io, basename='STATS_ETH')
hdr = eth.read_hdr(0)
eth.disassemble_hdr(hdr)
tc.append_log(3, '')
eth.ETH_read_setup()
eth.PCS_read_setup()
eth.MAC_read_setup()
tc.append_log(3, '')
def read_reg(tc,io,cmd): def read_reg(tc,io,cmd):
tc.set_section_id('COMMON_REG cnt_valid_udp_frm - ') tc.set_section_id('COMMON_REG cnt_valid_udp_frm - ')
tc.append_log(3, '>>>') tc.append_log(3, '>>>')
...@@ -341,9 +380,11 @@ Cmd['LED'] = (test_leds, 'using pi_debug_wave to set LEDs (access PIO_DEB ...@@ -341,9 +380,11 @@ Cmd['LED'] = (test_leds, 'using pi_debug_wave to set LEDs (access PIO_DEB
Cmd['PPSH'] = (test_ppsh, 'using pi_ppsh to read PPSH capture count (access PIO_PPS)','') Cmd['PPSH'] = (test_ppsh, 'using pi_ppsh to read PPSH capture count (access PIO_PPS)','')
Cmd['ETH'] = (test_eth, 'using pi_eth to read eth status','') Cmd['ETH'] = (test_eth, 'using pi_eth to read eth status','')
Cmd['CFG_BA'] = (conf_eth_BeamA, 'using pi_eth_OCB to configure BeamA','') Cmd['CFG_BA'] = (conf_eth_BeamA, 'using pi_eth_OCB to configure BeamA','')
Cmd['CFG_BB'] = (conf_eth_BeamB, 'using pi_eth_OCB to configure BeamB','')
Cmd['TST_BA'] = (test_eth_BeamA, 'using pi_eth_OCB to read BeamA status','') Cmd['TST_BA'] = (test_eth_BeamA, 'using pi_eth_OCB to read BeamA status','')
Cmd['CFG_BB'] = (conf_eth_BeamB, 'using pi_eth_OCB to configure BeamB','')
Cmd['TST_BB'] = (test_eth_BeamB, 'using pi_eth_OCB to read BeamB status','') Cmd['TST_BB'] = (test_eth_BeamB, 'using pi_eth_OCB to read BeamB status','')
Cmd['CFG_SS'] = (conf_eth_Stats, 'using pi_eth_OCB to configure Stats','')
Cmd['TST_SS'] = (test_eth_Stats, 'using pi_eth_OCB to read Stats status','')
Cmd['RD_REG'] = (read_reg, 'using pi_common_reg to read cnt_valid_udp_frm','') Cmd['RD_REG'] = (read_reg, 'using pi_common_reg to read cnt_valid_udp_frm','')
Cmd['REMU'] = (test_remu, 'using pi_remu to load user image (access REG_REMU)','') Cmd['REMU'] = (test_remu, 'using pi_remu to load user image (access REG_REMU)','')
Cmd['WDI'] = (test_wdi, 'using pi_wdi to reset to image in bank 0 (access REG_WDI)','') Cmd['WDI'] = (test_wdi, 'using pi_wdi to reset to image in bank 0 (access REG_WDI)','')
......
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