extended common_interval_monitor with offset_cnt field

libraries/base/common/src/vhdl/common_interval_monitor.vhd

@@ -41,14 +41,15 @@ ENTITY common_interval_monitor IS
     in_val        : IN  STD_LOGIC := '1';
     in_evt        : IN  STD_LOGIC;
     -- MM
-    interval_cnt  : OUT STD_LOGIC_VECTOR(g_interval_cnt_w-1 DOWNTO 0)
+    interval_cnt  : OUT STD_LOGIC_VECTOR(g_interval_cnt_w-1 DOWNTO 0);
+    clk_cnt       : OUT STD_LOGIC_VECTOR(g_interval_cnt_w-1 DOWNTO 0)
   );
 END common_interval_monitor;
 
 
 ARCHITECTURE rtl OF common_interval_monitor IS
 
-  SIGNAL clk_cnt          : STD_LOGIC_VECTOR(interval_cnt'RANGE);
+  SIGNAL i_clk_cnt        : STD_LOGIC_VECTOR(interval_cnt'RANGE);
   SIGNAL nxt_clk_cnt      : STD_LOGIC_VECTOR(interval_cnt'RANGE);
   SIGNAL i_interval_cnt   : STD_LOGIC_VECTOR(interval_cnt'RANGE);
   SIGNAL nxt_interval_cnt : STD_LOGIC_VECTOR(interval_cnt'RANGE);
@@ -56,34 +57,35 @@ ARCHITECTURE rtl OF common_interval_monitor IS
 BEGIN
 
   interval_cnt <= i_interval_cnt;
+  clk_cnt      <= i_clk_cnt;
 
   p_clk: PROCESS(clk, rst)
   BEGIN
     IF rst='1' THEN
-      clk_cnt        <= (OTHERS=>'1');
+      i_clk_cnt        <= (OTHERS=>'1');
       i_interval_cnt <= (OTHERS=>'1');
     ELSIF rising_edge(clk) THEN
-      clk_cnt        <= nxt_clk_cnt;
+      i_clk_cnt        <= nxt_clk_cnt;
       i_interval_cnt <= nxt_interval_cnt;
     END IF;
   END PROCESS;
 
-  p_counter : PROCESS(clk_cnt, i_interval_cnt, in_evt, in_val)
+  p_counter : PROCESS(i_clk_cnt, i_interval_cnt, in_evt, in_val)
   BEGIN
-    nxt_clk_cnt      <= clk_cnt;
+    nxt_clk_cnt      <= i_clk_cnt;
     nxt_interval_cnt <= i_interval_cnt;
     
     IF in_evt='1' THEN
-      -- If there is an in_evt pulse, then capture the clk_cnt into interval_cnt and restart clk_cnt
+      -- If there is an in_evt pulse, then capture the i_clk_cnt into interval_cnt and restart i_clk_cnt
       nxt_clk_cnt      <= (OTHERS=>'0');
-      nxt_interval_cnt <= INCR_UVEC(clk_cnt, 1);
-    ELSIF SIGNED(clk_cnt)=-1 THEN
-      -- If there occur no in_evt pulses, then clk_cnt will eventually stop at maximum (= -1)
+      nxt_interval_cnt <= INCR_UVEC(i_clk_cnt, 1);
+    ELSIF SIGNED(i_clk_cnt)=-1 THEN
+      -- If there occur no in_evt pulses, then i_clk_cnt will eventually stop at maximum (= -1)
       nxt_clk_cnt      <= (OTHERS=>'1');
       nxt_interval_cnt <= (OTHERS=>'1');
     ELSIF in_val='1' THEN
       -- Increment for valid clk cycles
-      nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
+      nxt_clk_cnt <= INCR_UVEC(i_clk_cnt, 1);
     END IF;
   END PROCESS;
   

libraries/io/ppsh/src/vhdl/ppsh.vhd

@@ -68,7 +68,7 @@ ENTITY ppsh IS
     pps_toggle     : OUT STD_LOGIC;           -- pps toggle level signal in clk domain (i.e. 0.5 Hz square wave)
     pps_stable     : OUT STD_LOGIC;           -- pps stable signal in clk domain
     capture_cnt    : OUT STD_LOGIC_VECTOR(ceil_log2(g_clk_freq)-1 DOWNTO 0);  -- counts the number of clk clock cycles between subsequent pps_ext pulses
-    offset_cnt     : OUT STD_LOGIC_VECTOR(ceil_log2(g_clk_freq)+1 DOWNTO 0);  -- counts the number of clk clock cycles between now and last pps_ext pulse
+    offset_cnt     : OUT STD_LOGIC_VECTOR(ceil_log2(g_clk_freq)-1 DOWNTO 0);  -- counts the number of clk clock cycles between now and last pps_ext pulse
     pps_stable_ack : IN  STD_LOGIC := '0';    -- pps stable acknowledge in clk domain
     capture_edge   : IN  STD_LOGIC := '0';                                    -- when '0' then clock pps_ext on rising edge of clk, else use falling edge of clk
     expected_cnt   : IN  STD_LOGIC_VECTOR(ceil_log2(g_clk_freq)-1 DOWNTO 0) := (OTHERS=> '1') -- expected number of clk clock cycles between subsequent pps_ext pulses
@@ -175,20 +175,10 @@ BEGIN
     in_val        => '1',
     in_evt        => pps_ext_revt,
     -- MM
-    interval_cnt  => i_capture_cnt
+    interval_cnt  => i_capture_cnt,
+    clk_cnt       => i_offset_cnt
   );
   
-  u_offset_cnt : ENTITY common_lib.common_counter
-  GENERIC MAP (
-    g_width => offset_cnt'LENGTH
-  )
-  PORT MAP (
-    rst           => rst,
-    clk           => clk,
-    cnt_clr       => pps_ext_revt,
-    count         => i_offset_cnt
-  );
-
   -- Output the pps_sys with extra pipelining to ease timing of pps_sys fan out
   u_pps_sys : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP (

libraries/io/ppsh/src/vhdl/ppsh_reg.vhd

@@ -72,7 +72,7 @@ ENTITY ppsh_reg IS
     st_pps_toggle     : IN  STD_LOGIC;
     st_pps_stable     : IN  STD_LOGIC;
     st_capture_cnt    : IN  STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0);  -- counts the number of clk clock cycles between subsequent pps_ext pulses
-    st_offset_cnt     : IN  STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)+1 DOWNTO 0);  -- counts the number of clk clock cycles between now and last pps_ext pulse
+    st_offset_cnt     : IN  STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0);  -- counts the number of clk clock cycles between now and last pps_ext pulse
     
     st_pps_stable_ack : OUT STD_LOGIC;
     
@@ -158,7 +158,7 @@ BEGIN
             sla_out.rddata(29 DOWNTO 0) <= RESIZE_UVEC(mm_expected_cnt, 30);
           WHEN 2 =>
             -- Read PPSH offset count
-            sla_out.rddata(31 DOWNTO 0) <= RESIZE_UVEC(mm_offset_cnt, 32);
+            sla_out.rddata(29 DOWNTO 0) <= RESIZE_UVEC(mm_offset_cnt, 30);
           WHEN OTHERS => NULL;  -- not used MM addresses
         END CASE;
       END IF;

libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd

@@ -56,6 +56,7 @@ ARCHITECTURE tb OF tb_ppsh IS
   SIGNAL pps_toggle       : STD_LOGIC;
   SIGNAL capture_edge     : STD_LOGIC;
   SIGNAL capture_cnt      : STD_LOGIC_VECTOR(ceil_log2(c_clk_freq)-1 DOWNTO 0);
+  SIGNAL offset_cnt       : STD_LOGIC_VECTOR(ceil_log2(c_clk_freq)-1 DOWNTO 0);
   
   -- Verify
   
@@ -160,7 +161,8 @@ BEGIN
     pps_toggle    => pps_toggle,
     -- MM control
     capture_edge  => capture_edge,
-    capture_cnt   => capture_cnt
+    capture_cnt   => capture_cnt,
+    offset_cnt    => offset_cnt
   );
 
   -----------------------------------------------------------------------------