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Commit 77ee4188 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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reorganized files and using only 1 hex file for init bg

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boards/uniboard1/designs/unb1_test/hdllib.cfg
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− 2
View file @ 77ee4188
......@@ -9,8 +9,8 @@ synth_files =
src/vhdl/qsys_unb1_test_pkg.vhd
src/vhdl/unb1_test_pkg.vhd
src/vhdl/mmm_unb1_test.vhd
src/vhdl/udp_stream_test.vhd
src/vhdl/ddr_stream_test.vhd
src/vhdl/udp_stream.vhd
src/vhdl/ddr_stream.vhd
src/vhdl/unb1_test.vhd
test_bench_files =
......
boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+ 0
− 14
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......@@ -17,22 +17,8 @@ synth_top_level_entity =
quartus_copy_files =
../../quartus/qsys_unb1_test.qsys .
../../src/hex/counter_data_128_0.hex ../..
../../src/hex/counter_data_128_1.hex ../..
../../src/hex/counter_data_128_2.hex ../..
../../src/hex/counter_data_128_3.hex ../..
../../src/hex/counter_data_128_4.hex ../..
../../src/hex/counter_data_32_0.hex ../..
../../src/hex/counter_data_32_1.hex ../..
../../src/hex/counter_data_32_2.hex ../..
../../src/hex/counter_data_32_3.hex ../..
../../src/hex/counter_data_32_4.hex ../..
../../src/hex/counter_data_64_0.hex ../..
../../src/hex/counter_data_64_1.hex ../..
../../src/hex/counter_data_64_2.hex ../..
../../src/hex/counter_data_64_3.hex ../..
../../src/hex/counter_data_64_4.hex ../..
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
......
boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg deleted 100644 → 0
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hdl_lib_name = unb1_test_lpbk
hdl_library_clause_name = unb1_test_lpbk_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
unb1_test_lpbk.vhd
test_bench_files =
tb_unb1_test_lpbk.vhd
synth_top_level_entity =
quartus_copy_files =
../../quartus/qsys_unb1_test.qsys .
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_0.hex ../..
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_1.hex ../..
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_2.hex ../..
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_0.hex ../..
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_1.hex ../..
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_2.hex ../..
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_0.hex ../..
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_1.hex ../..
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_2.hex ../..
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
../../quartus/unb1_test_pins.tcl
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_lpbk/qsys_unb1_test/synthesis/qsys_unb1_test.qip
boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/tb_unb1_test_lpbk.vhd deleted 100644 → 0
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Test bench for unb1_test_lpbk.
-- Description: see tb_unb1_test
LIBRARY IEEE, unb1_test_lib;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_unb1_test_lpbk IS
END tb_unb1_test_lpbk;
ARCHITECTURE tb OF tb_unb1_test_lpbk IS
BEGIN
u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
GENERIC MAP (
g_design_name => "unb1_test_lpbk"
);
END tb;
boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd deleted 100644 → 0
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, unb1_board_lib, unb1_test_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
ENTITY unb1_test_lpbk IS
GENERIC (
g_design_name : STRING := "unb1_test_lpbk"; -- use revision name = entity name = design name
g_design_note : STRING := "Test Design with loopback";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 7;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
--CLK : IN STD_LOGIC; -- System Clock - not used as the SOPC generates dp_clk.
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
sens_sc : INOUT STD_LOGIC;
sens_sd : INOUT STD_LOGIC;
-- 1GbE Control Interface
ETH_clk : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC
-- Transceiver clocks
--SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
-- Serial I/O
--SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
--SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
--SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
--SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
--SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
--BN_BI_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--BN_BI_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--BN_BI_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--BN_BI_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0)
);
END unb1_test_lpbk;
ARCHITECTURE str OF unb1_test_lpbk IS
BEGIN
u_revision : ENTITY unb1_test_lib.unb1_test
GENERIC MAP (
g_design_name => g_design_name,
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn
)
PORT MAP (
-- GENERAL
--CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- I2C Interface to Sensors
sens_sc => sens_sc,
sens_sd => sens_sd,
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- Transceiver clocks
SA_CLK => '0',
-- Serial I/O
SI_FN_0_TX => OPEN,
SI_FN_0_RX => (OTHERS => '0'),
SI_FN_1_TX => OPEN,
SI_FN_1_RX => (OTHERS => '0'),
SI_FN_2_TX => OPEN,
SI_FN_2_RX => (OTHERS => '0'),
SI_FN_3_TX => OPEN,
SI_FN_3_RX => (OTHERS => '0'),
SI_FN_0_CNTRL => OPEN,
SI_FN_1_CNTRL => OPEN,
SI_FN_2_CNTRL => OPEN,
SI_FN_3_CNTRL => OPEN,
SI_FN_RSTN => OPEN,
BN_BI_0_TX => OPEN,
BN_BI_0_RX => (OTHERS => '0'),
BN_BI_1_TX => OPEN,
BN_BI_1_RX => (OTHERS => '0'),
BN_BI_2_TX => OPEN,
BN_BI_2_RX => (OTHERS => '0'),
BN_BI_3_TX => OPEN,
BN_BI_3_RX => (OTHERS => '0')
);
END str;
boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/hdllib.cfg deleted 100644 → 0
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hdl_lib_name = unb1_test_qsys
hdl_library_clause_name = unb1_test_qsys_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
unb1_test_qsys.vhd
test_bench_files =
synth_top_level_entity =
quartus_copy_files =
../../quartus/qsys_unb1_test.qsys .
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_0.hex .
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_1.hex .
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_2.hex .
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_0.hex .
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_1.hex .
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_2.hex .
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_0.hex .
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_1.hex .
$UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_2.hex .
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
../../quartus/unb1_test_pins.tcl
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_qsys/qsys_unb1_test/synthesis/qsys_unb1_test.qip
boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/unb1_test_qsys.vhd deleted 100644 → 0
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, unb1_board_lib, unb1_test_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
ENTITY unb1_test_qsys IS
GENERIC (
g_design_name : STRING := "unb1_test_qsys"; -- use revision name = entity name = design name
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
--CLK : IN STD_LOGIC; -- System Clock - not used as the SOPC generates dp_clk.
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
sens_sc : INOUT STD_LOGIC;
sens_sd : INOUT STD_LOGIC;
-- 1GbE Control Interface
ETH_clk : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC;
-- Transceiver clocks
SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
-- Serial I/O
SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
BN_BI_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0)
);
END unb1_test_qsys;
ARCHITECTURE str OF unb1_test_qsys IS
BEGIN
u_revision : ENTITY unb1_test_lib.unb1_test
GENERIC MAP (
g_design_name => g_design_name,
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn
)
PORT MAP (
-- GENERAL
--CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- I2C Interface to Sensors
sens_sc => sens_sc,
sens_sd => sens_sd,
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- Transceiver clocks
SA_CLK => SA_CLK,
-- Serial I/O
SI_FN_0_TX => SI_FN_0_TX,
SI_FN_0_RX => SI_FN_0_RX,
SI_FN_1_TX => SI_FN_1_TX,
SI_FN_1_RX => SI_FN_1_RX,
SI_FN_2_TX => SI_FN_2_TX,
SI_FN_2_RX => SI_FN_2_RX,
SI_FN_3_TX => SI_FN_3_TX,
SI_FN_3_RX => SI_FN_3_RX,
SI_FN_0_CNTRL => SI_FN_0_CNTRL,
SI_FN_1_CNTRL => SI_FN_1_CNTRL,
SI_FN_2_CNTRL => SI_FN_2_CNTRL,
SI_FN_3_CNTRL => SI_FN_3_CNTRL,
SI_FN_RSTN => SI_FN_RSTN,
BN_BI_0_TX => BN_BI_0_TX,
BN_BI_0_RX => BN_BI_0_RX,
BN_BI_1_TX => BN_BI_1_TX,
BN_BI_1_RX => BN_BI_1_RX,
BN_BI_2_TX => BN_BI_2_TX,
BN_BI_2_RX => BN_BI_2_RX,
BN_BI_3_TX => BN_BI_3_TX,
BN_BI_3_RX => BN_BI_3_RX
);
END str;
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:0400000000000000FC
:0400010000000001FA
:0400020000000002F8
:0400030000000003F6
:0400040000000004F4
:0400050000000005F2
:0400060000000006F0
:0400070000000007EE
:0400080000000008EC
:0400090000000009EA
:04000A000000000AE8
:04000B000000000BE6
:04000C000000000CE4
:04000D000000000DE2
:04000E000000000EE0
:04000F000000000FDE
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