Renamed mag_10.vhd into io_mac_10g.vhd. The g_nof_channels > 1 support still...

Renamed mag_10.vhd into io_mac_10g.vhd. The g_nof_channels > 1 support still need to be added, but maybe this io_mac_10g library is not needed at all.

libraries/io/mac_10g/hdllib.cfg

-hdl_lib_name = mac_10g
-hdl_library_clause_name = mac_10g_lib
+hdl_lib_name = io_mac_10g
+hdl_library_clause_name = io_mac_10g_lib
 hdl_lib_uses = technology tech_mac_10g common dp
 hdl_lib_technology = 
 
@@ -7,6 +7,6 @@ build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
-    mac_10g.vhd
+    io_mac_10g.vhd
 
 test_bench_files =

libraries/io/mac_10g/mac_10g.vhd → libraries/io/mac_10g/io_mac_10g.vhd

@@ -25,7 +25,7 @@
 -- Description:
 --   See description of tech_mac_10g.
 --
---   The wrapper is made because it brings the mac_10g at the same hierarchy
+--   The wrapper is made because it brings the io_mac_10g at the same hierarchy
 --   level as tr_xaui, which are then used in tr_10GbE. The wrapper also allows
 --   for glue logic that may be needed in future and would fit better here than
 --   in tech_mac_10g.
@@ -42,38 +42,43 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_interface_layers_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
 
-ENTITY mac_10g IS
+ENTITY io_mac_10g IS
   GENERIC (
     g_technology          : NATURAL := c_tech_select_default;
+    g_nof_channels        : NATURAL := 1;
     g_pre_header_padding  : BOOLEAN := FALSE
   );
   PORT (
     -- MM
     mm_clk            : IN  STD_LOGIC;
     mm_rst            : IN  STD_LOGIC;
-    mac_mosi         : IN  t_mem_mosi;  -- MAC CSR = control status register
-    mac_miso         : OUT t_mem_miso;
+    csr_mosi          : IN  t_mem_mosi;  -- CSR = control status register
+    csr_miso          : OUT t_mem_miso;
 
     -- ST
-    tx_clk           : IN  STD_LOGIC;   -- 156.25 MHz local reference
+    tx_clk_312        : IN  STD_LOGIC := '0';   -- 312.5 MHz
+    tx_clk_156        : IN  STD_LOGIC;          -- 156.25 MHz local reference
     tx_rst            : IN  STD_LOGIC;
     tx_snk_in         : IN  t_dp_sosi;   -- 64 bit data
     tx_snk_out        : OUT t_dp_siso; 
     
-    rx_clk           : IN  STD_LOGIC;   -- 156.25 MHz from rx phy
+    rx_clk_312        : IN  STD_LOGIC := '0';   -- 312.5 MHz
+    rx_clk_156        : IN  STD_LOGIC;          -- 156.25 MHz from rx phy
     rx_rst            : IN  STD_LOGIC;
     rx_src_out        : OUT t_dp_sosi;   -- 64 bit data
     rx_src_in         : IN  t_dp_siso; 
     
     -- XGMII
+    xgmii_link_status : OUT STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0);  -- 2 bit
     xgmii_tx_data     : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0);  -- 72 bit
     xgmii_rx_data     : IN  STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0)   -- 72 bit
   );
-END mac_10g;
+END io_mac_10g;
 
 
-ARCHITECTURE str OF mac_10g IS
+ARCHITECTURE str OF io_mac_10g IS
 
 BEGIN
  
@@ -90,17 +95,20 @@ BEGIN
     csr_miso          => mac_miso,
 
     -- ST
-    tx_clk           => tx_clk,
+    tx_clk_312        => tx_clk_312,
+    tx_clk_156        => tx_clk_156,
     tx_rst            => tx_rst,
-    tx_snk_in        => tx_snk_in,
+    tx_snk_in         => tx_snk_in,    -- 64 bit data
     tx_snk_out        => tx_snk_out, 
     
-    rx_clk           => rx_clk,
+    rx_clk_312        => rx_clk_312,
+    rx_clk_156        => rx_clk_156,
     rx_rst            => rx_rst,
-    rx_src_out       => rx_src_out,
+    rx_src_out        => rx_src_out,   -- 64 bit data
     rx_src_in         => rx_src_in,
     
     -- XGMII
+    xgmii_link_status => xgmii_link_status,
     xgmii_tx_data     => xgmii_tx_data,
     xgmii_rx_data     => xgmii_rx_data
   );