Use hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master...

Use hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master instead of hdl_lib_excludes.

applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg

@@ -2,10 +2,6 @@ hdl_lib_name = apertif_unb1_fn_beamformer_base
 hdl_library_clause_name = apertif_unb1_fn_beamformer_base_lib
 hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif tech_ddr io_ddr
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master 
-                   ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
 
 synth_files =     
     ../../../../../../libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd 

applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_bf_tp/hdllib.cfg

@@ -2,9 +2,7 @@ hdl_lib_name = apertif_unb1_fn_beamformer_bg_bf_tp
 hdl_library_clause_name = apertif_unb1_fn_beamformer_bg_bf_tp_lib
 hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif tech_ddr io_ddr
 hdl_lib_technology = ip_stratixiv 
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
-                   ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =     
     ../../../../../../libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd 

applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_tp/hdllib.cfg

@@ -2,9 +2,7 @@ hdl_lib_name = apertif_unb1_fn_beamformer_bg_tp
 hdl_library_clause_name = apertif_unb1_fn_beamformer_bg_tp_lib
 hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif tech_ddr io_ddr
 hdl_lib_technology = ip_stratixiv 
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
-                   ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =     
     ../../../../../../libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd 

applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg

 hdl_lib_name = apertif_unb1_fn_beamformer_trans
 hdl_library_clause_name = apertif_unb1_fn_beamformer_trans_lib
-hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif tech_ddr io_ddr diag_lib
-hdl_lib_technology = ip_stratixiv 
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
-                   ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-                   ip_stratixiv_ddr3_uphy_16g_dual_rank_800
+hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif tech_ddr io_ddr diag
+hdl_lib_technology = ip_stratixiv
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =    
     ../../../../../../libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd